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Category: System On Chip IP Cores (17)

Assembler With VHDL User-defined Commands (AVUC)

Here is proposed a method to implement short structured programs inside an FPGA. The novelty of the proposed method resides in that the commands…

License : LGPL
Language : VHDL

EPC RFID Transponder

n/a

License : LGPL
Language : VHDL

AMBAtm Specification Compliant AHB System Generator

The intention is to provide an easy way to configure, create and simulate a "complete" AHB system. The main block is the "AHB…

License : LGPL
Language : VHDL

AXI4 Transactor and Bus Functional Model Implementation in VHDL

This project implements the AXI4 transaction-level model (TLM) and bus functional model (BFM) in VHDL. Currently, only the AXI4-Stream Master…

License : LGPL
Language : VHDL

CPU Lecture SoC in VHDL

Overview This is a lecture about designing a SoC in VHDL. Everything runs under Linux - no more Windows! Check it out and then start at the file…

License : GPL
Language : VHDL

16-bit Experimental Unstable CPU with a Simple Bus System

A simple 16-bit microprocessor together with a simple bus system. It utilises the Xilinx dual port ram features to be able to fetch instructions…

License : LGPL
Language : VHDL

Wishbone to I2C Controller Wrapper

Short: virtually convert an I2C slave into a WISHBONE slave This is a wrapper for the I2C controller core by Richard Herveille…

License : LGPL
Language : VHDL

MIPS I 512 MBit DDR Ram layer 2 SoC

The following components are implemented and tested on silicon: MIPS I(tm) CPU @ 50MHz Intel StratFlash PS/2 Keyboard 100x37 8-Color Text-VGA…

License : GPL
Language : VHDL

NoCem - Synthesizable VHDL Network on Chip Emulator

A Network on Chip Emulation Tool, NoCem is a body of VHDL code configurable by a toplevel package file that can create a variety of Network on…

License : GPL
Language : VHDL

Programmed Data Processor-1 (PDP-1) Reimplementation Using FPGA

PDP-1 reimplementation using an FPGA. The goal is to run old software like Spacewar!, the music compiler, and Expensive Typewriter on current FPGA…

License : LGPL
Language : VHDL

Real-time Image Component Labeling and Feature Extraction

INFO The project is RT level design of image component labeling and feature extraction. The design is captured in VHDL. The architecture is…

License : LGPL
Language : VHDL

RTF68k System-on-Chip (SOC) Using Wishbone Bus Interface

This is a complete system-on-a-chip. Developed on a Diligent Spartan3e board, the SOC includes CPU (TG68), bitmap and text displays, PSG, keyboard…

License : LGPL
Language : Verilog & VHDL

Soft Multiprocessor Architecture on FPGA

Soft Multiprocessor on FPGA is becoming more attractive as the design cost and NRE soaring up in deep-submicron age, especially for high…

License : GPL
Language : VHDL

STORM SoC (System on Chip) with 32-bit Wishbone Bus System

Welcome to the STORM SoC project! This is an FPGA/evaluation board-independent, complete system on chip implementation based on the STORM CORE…

License : GPL
Language : VHDL

SBA - Simple Bus Architecture System Creator

The Simple Bus Architecture (SBA) is an architecture made up software tools and intellectual property cores (IP Cores) interconnected by buses set…

License : LGPL
Language : VHDL

System05 - VHDL 6805 Compatible Core

6805 compatible CPU Core. Does not have any of the standard 6805 on chip peripherals at this stage other than the parallel I/O port. This was the…

License : GPL
Language : VHDL

Simulated and Synthesized Wishbone Out Port From B3 Spec

Are you using Wishbone, do you need some simple 'slaves' to test your bus with ? Well, the Wishbone spec, appendix B3, has VHDL examples of…

License : LGPL
Language : VHDL