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Category: System On Chip IP Cores (20)

Generic AHB Matrix

Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according…

License : LGPL
Language : Verilog

Generic AXI Interconnect Fabric

Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI…

License : LGPL
Language : Verilog

Generic AXI To AHB Bridge

Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB…

License : LGPL
Language : Verilog

Generic AXI To APB Bridge

Generic AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error,…

License : LGPL
Language : Verilog

Or1k SoC Altera Embedded Dev Kit for OpenRISC 1200 Implementation

This project is to implement a SoC of using OpenRISC 1200 and many open source IP cores from opencores.org on Nios II Embedded Evaluation Kit…

License : LGPL
Language : Verilog

Asynchronous Spatial Division Multiplexing Router for NoCs

Asynchronous Spatial Division Multiplexing Router for On-Chip Networks Version: 0.2 On-chip networks or networks-on-chip (NoCs) are the on-chip…

License : LGPL
Language : Verilog

32/64 bits AHB Master DMA Core

Single channel 32 or 64 bit AHB master DMA core. Supports simultaneous read and write, command lists, peripheral control, timeouts and endianess…

License : LGPL
Language : Verilog

Minimal OpenRISC System on Chip Implementation

The Minimal OpenRISC System on Chip is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation…

License : LGPL
Language : Verilog

32/64 bits AXI master DMA Core

Single channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control,…

License : LGPL
Language : Verilog

Generic APB Register File Generator

Generic APB register file generator. Creates Verilog source, C header file and HTML documentation, from an Excel worksheet. The source files are…

License : LGPL
Language : Verilog

ProNoC GUI MCSoC Generator

Project Summary Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC…

License : LGPL
Language : Verilog

Keras to FPGA SoC

Description Implements Dense ANN that can directly use the weights from Keras. Still need to add SoftMax, MaxPooling, Conv2D & LSTM The url of…

License : LGPL
Language : Verilog

M16C5x Soft-core Processor

This project demonstrates the use of the P16C5x soft-processor core, found elsewhere on opencores.org, in a system-on-chip. The project targets a…

License : LGPL
Language : Verilog

Next186 Core SoC PC

PC AT SoC based on Next186 core. CPU runs at up to 80 MHz (80 MIPS), up to 64MB of RAM, HMA available. Able to run DOS6.22, FreeDos, Windows3.0,…

License : LGPL
Language : Verilog

4-way set associative Next186MP3 Decoder

This is an evolution of my previous project, Next186SoC PC, able to play MP3 files in real time (any bitrate). It is written in Verilog, and it…

License : LGPL
Language : Verilog

OC - H.264 Encoder SoC Solution Based on Open-source Blocks

The goal is to develop an H.264 Encoder SoC (System-on-Chip) solution based only on open-source blocks. Status 2009-08-24: A software-team is…

License : LGPL
Language : Verilog

OMS8051 MINI - Open 8051 Based Embedded System

Is a Open 8051 based Embededed System, Include a 8051 with Following SubSystem 32K Program Memory 32K Data Memory 1x I2C Master 1x I2C Slave 1x SPI…

License : LGPL
Language : Verilog

Modified Project Oberon for SDRAM and DDRAM Interface

Project Oberon http://www.projectoberon.com modified to use SDRAM instead of static RAM Static RAM is old technology in FPGA world, and 1MB 32bit…

License : LGPL
Language : Verilog

RTF68k System-on-Chip (SOC) Using Wishbone Bus Interface

This is a complete system-on-a-chip. Developed on a Diligent Spartan3e board, the SOC includes CPU (TG68), bitmap and text displays, PSG, keyboard…

License : LGPL
Language : Verilog & VHDL

Zorro Bus to Wishbone Bridge

This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families,…

License : LGPL
Language : Verilog