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Category: System On Chip IP Cores (44)

Assembler With VHDL User-defined Commands (AVUC)

Here is proposed a method to implement short structured programs inside an FPGA. The novelty of the proposed method resides in that the commands…

License : LGPL
Language : VHDL

EPC RFID Transponder

n/a

License : LGPL
Language : VHDL

Generic AHB Matrix

Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according…

License : LGPL
Language : Verilog

Generic AXI Interconnect Fabric

Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI…

License : LGPL
Language : Verilog

Generic AXI To AHB Bridge

Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB…

License : LGPL
Language : Verilog

Generic AXI To APB Bridge

Generic AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error,…

License : LGPL
Language : Verilog

Or1k SoC Altera Embedded Dev Kit for OpenRISC 1200 Implementation

This project is to implement a SoC of using OpenRISC 1200 and many open source IP cores from opencores.org on Nios II Embedded Evaluation Kit…

License : LGPL
Language : Verilog

Asynchronous Spatial Division Multiplexing Router for NoCs

Asynchronous Spatial Division Multiplexing Router for On-Chip Networks Version: 0.2 On-chip networks or networks-on-chip (NoCs) are the on-chip…

License : LGPL
Language : Verilog

32/64 bits AHB Master DMA Core

Single channel 32 or 64 bit AHB master DMA core. Supports simultaneous read and write, command lists, peripheral control, timeouts and endianess…

License : LGPL
Language : Verilog

AMBAtm Specification Compliant AHB System Generator

The intention is to provide an easy way to configure, create and simulate a "complete" AHB system. The main block is the "AHB…

License : LGPL
Language : VHDL

Minimal OpenRISC System on Chip Implementation

The Minimal OpenRISC System on Chip is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation…

License : LGPL
Language : Verilog

32/64 bits AXI master DMA Core

Single channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control,…

License : LGPL
Language : Verilog

AXI4 Transactor and Bus Functional Model Implementation in VHDL

This project implements the AXI4 transaction-level model (TLM) and bus functional model (BFM) in VHDL. Currently, only the AXI4-Stream Master…

License : LGPL
Language : VHDL

CMOD S6 SoC for ZipCPU Soft Core Implementation

This CMOD-S6 SoC grew out of the desire to demonstrate that a useful ZipCPU soft core implementation could be made in a very small space. In…

License : GPL
Wishbone Version : B.4
Language : Verilog

CPU Lecture SoC in VHDL

Overview This is a lecture about designing a SoC in VHDL. Everything runs under Linux - no more Windows! Check it out and then start at the file…

License : GPL
Language : VHDL

16-bit Experimental Unstable CPU with a Simple Bus System

A simple 16-bit microprocessor together with a simple bus system. It utilises the Xilinx dual port ram features to be able to fetch instructions…

License : LGPL
Language : VHDL

Generic APB Register File Generator

Generic APB register file generator. Creates Verilog source, C header file and HTML documentation, from an Excel worksheet. The source files are…

License : LGPL
Language : Verilog

Wishbone to I2C Controller Wrapper

Short: virtually convert an I2C slave into a WISHBONE slave This is a wrapper for the I2C controller core by Richard Herveille…

License : LGPL
Language : VHDL

ProNoC GUI MCSoC Generator

Project Summary Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC…

License : LGPL
Language : Verilog

Keras to FPGA SoC

Description Implements Dense ANN that can directly use the weights from Keras. Still need to add SoftMax, MaxPooling, Conv2D & LSTM The url of…

License : LGPL
Language : Verilog