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Category: Testing / Verification IP Cores (3)

EziDebug - Easy-to-use Versatile Logic Simulation Tool

EziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in…

License : LGPL
Language : C/C++

JTAG Chains with JAM STAPL Player

Converts Raspberry Pi into a JTAG programmer (STAPL protocol). Supports two JTAG chains through 26-pin RPi GPIO P1 connector. The TCK rate is…

License : LGPL
Language : C/C++

Constrained Random Test Generator

Constrained random testing enables us to cover many more system behaviors through random input variations, random fault injections, and automatic…

License : LGPL
Language : C/C++