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Category: Uncategorized IP Cores (48)

2D Game Console on Altera DE2-115

A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…

License : LGPL
Language : Verilog & VHDL

Library of Commonly Used Base Functions

About this core This is a collection of commonly used base functions, used in all of ASTRONs other cores. These source files can work in any…

License : LGPL
Language : VHDL

VHDL 8254 Timer Using Synchronous Processor Interface

a VHDL version of the Intel 8254 timer. Note: uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.…

Language : VHDL

16x2 LCD controller for Xilinx

Controller for 16 character - 2 line LCD displays as used on various Xilinx evaluation boards. Features - 4-bit LCD data interface - One…

License : LGPL
Language : VHDL

2nd order Sigma-Delta DAC

Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.…

License : Others
Language : VHDL

VHDL 6532 RIOT (RAM-I/O-TIMER)

VHDL implementation of the 6532 RIOT (RAM-I/O-TIMER) Like the original chip from Mostek/Rockwell, this component is 6500/6800 bus compatible. The…

License : Others
Language : VHDL

Artificial Intelligence System Using FGPA/ASIC

The Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time…

License : Others
Language : VHDL

BigCounter for Xilinx FGPA

Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic Features Designed for…

License : GPL
Language : VHDL

Open Source FPGA Bitcoin Miner for Altera and Xilinx

n/a

License : LGPL
Language : VHDL

RFC 1951 - DEFLATE Data Compression Algorithm

A VHDL implementation of the open DEFLATE data compression algorithm. The DEFLATE standard is specified in RFC 1951 and was jointly developed by…

License : GPL
Language : VHDL

First File Reader on FAT16 File System

The aim of this Core is to track the first file saved into a FAT16 volume and to read the information from it offering those data to a Wishbone bus…

Language : VHDL

Discrete Wavelet Transform Co-processor on Still Image

This core implements Forward and Inverse Discrete Wavelet Transform (FDWT and IDWT) on still image. Wavelet LeGall 5/3 is selected in design. The…

Language : VHDL

G729A Codec for 16-bit LPCM Audio

G.729A codec core performs encoding and decoding of 16-bit LPCM audio samples according to ITU-T G.729A standard. The codec core supports multiple…

License : LGPL
Language : VHDL

Fuzzy Logic Hardware Accelerator Wishbone Compatible

This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix…

License : GPL
Language : VHDL

XmatchPro High-speed Lossless Data Compressor

Benefits of data compression The use of lossless data compression can bring about a number of increasingly important benefits to an electronic…

License : LGPL
Language : VHDL

General-purpose FPGA Pulse-processing Algorithm

n/a

License : LGPL
Language : VHDL

Dynamic Vectorial Generator

Vectorial generator: -Interface: bit or bus -Configuration: dynamic -Applications: waveform generator, serial or parallel communication Examples:…

License : Others
Language : VHDL

Efficient Hardware Looping Unit

Hardware looping unit Tha main purpose of the hardware looping unit (HWLU) is to enhance program control units found in modern microprocessors, by…

License : GPL
Language : VHDL

IMA ADPCM Sound Compressor with Testbench

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The…

License : GPL
Language : VHDL

Keyboard Controller with Simple Debounce Algorithm

The controller scans the keyboard by making a different column in "rows" logic-0 therefor the inputs "cols" have to be PULL-UP…

License : GPL
Language : VHDL