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Category: Uncategorized IP Cores (47)

Configurator

This application parses a Verilog define file and presents a GUI to the user

License : LGPL
Language : Verilog

Gsc

Description of project.. Features - feature1 - feature1.1 -feature1.2 -feature2

License : GPL
Language : Verilog

2D Game Console on Altera DE2-115

A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…

License : LGPL
Language : Verilog & VHDL

An Alternative Oscilloscope (AlternaScope)

AlternaScope provides a cheap alternative to expensive oscilloscopes; Using a VGA display and a simple mouse interface, a user can use this scope…

Language : Verilog

Adjustable Frequency Divider

Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…

License : LGPL
Language : Verilog

Programmable Sound Generator AY-3-8910 Compatible Module

This module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music.

License : GPL
Language : Verilog

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…

License : LGPL
Wishbone Version : B.4
Language : Verilog

Simple backtracking 9x9 Sudoku Solver in Verilog

Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C…

License : BSD
Language : Verilog

BU PACMAN Game with Advanced Digital Design Using Verilog

This is for the final project of EC551 Advanced Digital Design using Verilog, a course offered in Boston University. It's basically the classic…

License : GPL
Language : Verilog

Boundaries: Glitch-free Clock Switch Circuit

This project is a collection of small designs involved with clock boundaries. The clock_switch designs are based on an eetimes article. The…

Language : Verilog

Computer Operating Properly : Watchdog Timer Module

The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two…

License : BSD
Language : Verilog

Bubble Sort Module in Verilog

simple fast bubble sort module in verilog

License : LGPL
Language : Verilog

DNA Sequence Alignment Accelerator

This is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap…

License : LGPL
Language : Verilog

Cray-2-Reboot for FPGAs

Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot The goal of this project is to make a clock and gate equivalent…

License : LGPL
Language : Verilog

MMC Card FPGA Configuration Controller

IP Core for FPGA Configuration Controller from MMC Card. Can configure an FPGA in serial mode from continous blocks stored on MMC Card. Smallest…

Language : Verilog

Verilog Code LCD Block

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

GroundHog 2009 Repository - Benchmark Suite For Mobile Apps

GroundHog 2009 is a benchmark suite for reconfigurable architectures in the mobile domain. The benchmark suite can be downloaded from…

License : Others
Language : Verilog

Interrupt Controller 68000

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

OPL3 20 - Yamaha OPL3 (YMF262) FM Synthesizer Chip

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer chip. Design is complete and working on the Digilent ZYBO…

License : LGPL
Language : Verilog

16-Bit Programmable Interval Timer Module

The Programmable Interval Timer Module, PIT, is a simple timer to generate a periodic signal for a microcontroller system. This signal may be used…

License : BSD
Language : Verilog