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Introducing Calibre nmLVS-Recon
This application parses a Verilog define file and presents a GUI to the user
Description of project.. Features - feature1 - feature1.1 -feature1.2 -feature2
A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…
AlternaScope provides a cheap alternative to expensive oscilloscopes; Using a VGA display and a simple mouse interface, a user can use this scope…
Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…
This module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music.
AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…
Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C…
This is for the final project of EC551 Advanced Digital Design using Verilog, a course offered in Boston University. It's basically the classic…
This project is a collection of small designs involved with clock boundaries. The clock_switch designs are based on an eetimes article. The…
The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two…
simple fast bubble sort module in verilog
This is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap…
Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot The goal of this project is to make a clock and gate equivalent…
IP Core for FPGA Configuration Controller from MMC Card. Can configure an FPGA in serial mode from continous blocks stored on MMC Card. Smallest…
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GroundHog 2009 is a benchmark suite for reconfigurable architectures in the mobile domain. The benchmark suite can be downloaded from…
Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer chip. Design is complete and working on the Digilent ZYBO…
The Programmable Interval Timer Module, PIT, is a simple timer to generate a periodic signal for a microcontroller system. This signal may be used…
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