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Category: Uncategorized IP Cores (7)

Simple backtracking 9x9 Sudoku Solver in Verilog

Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C…

License : BSD
Language : Verilog

Computer Operating Properly : Watchdog Timer Module

The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two…

License : BSD
Language : Verilog

16-Bit Programmable Interval Timer Module

The Programmable Interval Timer Module, PIT, is a simple timer to generate a periodic signal for a microcontroller system. This signal may be used…

License : BSD
Language : Verilog

Scalable Synchronous Round-robin Arbiter

A scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speeds with up to hundreds of request lines, and it…

License : BSD
Language : Verilog

Simple Implementation of FM Receiver

Simple FM Receiver Simple implementation of FM Receiver to demodulate square wave signal modulated in FM. This design uses PLL to demodulate FM…

License : BSD
Language : VHDL

Automatic Latency Equalizer For Pipelined Designs Implemented In VHDL

The pipelined architecture is often used in high speed FPGA cores. In complex designs data processing is often splitted into multiple paths…

License : BSD
Language : VHDL

CDC Micro FIFO

Clock Domain Crossing micro FIFO (Verilog/SystemVerilog): cdc_ufifo provide an minimalist fifo. Most advantage - not use RAM blocks. it can be 4…

License : BSD
Language : Verilog