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Category: Uncategorized IP Cores (71)

Configurator

This application parses a Verilog define file and presents a GUI to the user

License : LGPL
Language : Verilog

Gsc

Description of project.. Features - feature1 - feature1.1 -feature1.2 -feature2

License : GPL
Language : Verilog

2D Game Console on Altera DE2-115

A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…

License : LGPL
Language : Verilog & VHDL

Advanced Debug Interface for Multi-device JTAG Chains

The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a…

License : LGPL
Language : Other

Library of Commonly Used Base Functions

About this core This is a collection of commonly used base functions, used in all of ASTRONs other cores. These source files can work in any…

License : LGPL
Language : VHDL

16x2 LCD controller for Xilinx

Controller for 16 character - 2 line LCD displays as used on various Xilinx evaluation boards. Features - 4-bit LCD data interface - One…

License : LGPL
Language : VHDL

Adjustable Frequency Divider

Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…

License : LGPL
Language : Verilog

Programmable Sound Generator AY-3-8910 Compatible Module

This module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music.

License : GPL
Language : Verilog

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…

License : LGPL
Wishbone Version : B.4
Language : Verilog

BU PACMAN Game with Advanced Digital Design Using Verilog

This is for the final project of EC551 Advanced Digital Design using Verilog, a course offered in Boston University. It's basically the classic…

License : GPL
Language : Verilog

BigCounter for Xilinx FGPA

Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic Features Designed for…

License : GPL
Language : VHDL

Open Source FPGA Bitcoin Miner for Altera and Xilinx

n/a

License : LGPL
Language : VHDL

FGPA Connect6 Solver

CONNECT-6 SOLVER Connect-6 is usually played on a 19 × 19 GO Board, with each player having either black or white pieces. The Black starts…

License : GPL
Language : C/C++

Bubble Sort Module in Verilog

simple fast bubble sort module in verilog

License : LGPL
Language : Verilog

RFC 1951 - DEFLATE Data Compression Algorithm

A VHDL implementation of the open DEFLATE data compression algorithm. The DEFLATE standard is specified in RFC 1951 and was jointly developed by…

License : GPL
Language : VHDL

DNA Sequence Alignment Accelerator

This is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap…

License : LGPL
Language : Verilog

Cray-2-Reboot for FPGAs

Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot The goal of this project is to make a clock and gate equivalent…

License : LGPL
Language : Verilog

G729A Codec for 16-bit LPCM Audio

G.729A codec core performs encoding and decoding of 16-bit LPCM audio samples according to ITU-T G.729A standard. The codec core supports multiple…

License : LGPL
Language : VHDL

Fuzzy Logic Hardware Accelerator Wishbone Compatible

This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix…

License : GPL
Language : VHDL

Verilog Code LCD Block

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog