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Category: Uncategorized IP Cores (51)

Configurator

This application parses a Verilog define file and presents a GUI to the user

License : LGPL
Language : Verilog

2D Game Console on Altera DE2-115

A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…

License : LGPL
Language : Verilog & VHDL

Advanced Debug Interface for Multi-device JTAG Chains

The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a…

License : LGPL
Language : Other

Library of Commonly Used Base Functions

About this core This is a collection of commonly used base functions, used in all of ASTRONs other cores. These source files can work in any…

License : LGPL
Language : VHDL

16x2 LCD controller for Xilinx

Controller for 16 character - 2 line LCD displays as used on various Xilinx evaluation boards. Features - 4-bit LCD data interface - One…

License : LGPL
Language : VHDL

Adjustable Frequency Divider

Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…

License : LGPL
Language : Verilog

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…

License : LGPL
Wishbone Version : B.4
Language : Verilog

Open Source FPGA Bitcoin Miner for Altera and Xilinx

n/a

License : LGPL
Language : VHDL

Bubble Sort Module in Verilog

simple fast bubble sort module in verilog

License : LGPL
Language : Verilog

DNA Sequence Alignment Accelerator

This is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap…

License : LGPL
Language : Verilog

Cray-2-Reboot for FPGAs

Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot The goal of this project is to make a clock and gate equivalent…

License : LGPL
Language : Verilog

G729A Codec for 16-bit LPCM Audio

G.729A codec core performs encoding and decoding of 16-bit LPCM audio samples according to ITU-T G.729A standard. The codec core supports multiple…

License : LGPL
Language : VHDL

Verilog Code LCD Block

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

XmatchPro High-speed Lossless Data Compressor

Benefits of data compression The use of lossless data compression can bring about a number of increasingly important benefits to an electronic…

License : LGPL
Language : VHDL

General-purpose FPGA Pulse-processing Algorithm

n/a

License : LGPL
Language : VHDL

Interrupt Controller 68000

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

LFSR Counter Generator Up to 63 bit, Cross-Platform Compatible

LFSR Counter Generator is a command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The…

License : LGPL
Language : C/C++

Oscilloscope VHDL for Xilinx Spartan-3E at 160MSPS

This is an experimental oscilloscope VHDL design working on the Xilinx Spartan-3E starter board. The analog signal is sampled with a TI ADC08200…

License : LGPL
Language : VHDL

LPD8806 RGB LED String Driver in VHDL

Have you ever wanted to add some color to your project? Then this might be your answer. The LPD8806 RGB LED strings are available for low cost from…

License : LGPL
Language : VHDL

Configurable Modular Oscilloscope Function

The aim of the project is to develop oscilloscope functions (conversion control, trigger, FFT, ...) in several cores and implement a usefull…

License : LGPL
Language : VHDL