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Category: Uncategorized IP Cores (7)

2nd order Sigma-Delta DAC

Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.…

License : Others
Language : VHDL

VHDL 6532 RIOT (RAM-I/O-TIMER)

VHDL implementation of the 6532 RIOT (RAM-I/O-TIMER) Like the original chip from Mostek/Rockwell, this component is 6500/6800 bus compatible. The…

License : Others
Language : VHDL

Artificial Intelligence System Using FGPA/ASIC

The Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time…

License : Others
Language : VHDL

Dynamic Vectorial Generator

Vectorial generator: -Interface: bit or bus -Configuration: dynamic -Applications: waveform generator, serial or parallel communication Examples:…

License : Others
Language : VHDL

GroundHog 2009 Repository - Benchmark Suite For Mobile Apps

GroundHog 2009 is a benchmark suite for reconfigurable architectures in the mobile domain. The benchmark suite can be downloaded from…

License : Others
Language : Verilog

Turbo/Toy System Verilog Compiler

n/a

License : Others
Language : Bluespec

A VHDL 6530 RRIOT

VHDL implementation of the 6530 RRIOT (ROM-RAM-I/O-TIMER) Released under EUPL Licence (LGPL compatible). , ROM (1024 x 8) RAM (64 x 8) Two parallel…

License : Others
Language : VHDL