Or try an example search: BCD Adder
Introducing Calibre nmLVS-Recon
Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.…
VHDL implementation of the 6532 RIOT (RAM-I/O-TIMER) Like the original chip from Mostek/Rockwell, this component is 6500/6800 bus compatible. The…
The Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time…
Vectorial generator: -Interface: bit or bus -Configuration: dynamic -Applications: waveform generator, serial or parallel communication Examples:…
GroundHog 2009 is a benchmark suite for reconfigurable architectures in the mobile domain. The benchmark suite can be downloaded from…
n/a
VHDL implementation of the 6530 RRIOT (ROM-RAM-I/O-TIMER) Released under EUPL Licence (LGPL compatible). , ROM (1024 x 8) RAM (64 x 8) Two parallel…
Don't have an AAC account? Create one now.
Forgot your password? Click here.