Search our IC Design Center for IP Cores and IC Design Related Content.

Or try an example search: 8 bit multiplier

Category: Video Controller IP Cores (16)

AXI4 To VGA Frame Buffer With Linux Driver

This design is very simple in one verilog file. There is 2 version of the design : RGB332 (one pixel is one byte) and RGB565 (one pixel is 2 bytes)…

License : LGPL
Language : Verilog

CCITT Group 4 (TIFF) Lossless Compression

This project considers a hardware implementation of the CCITT group 4(also known as fax4 or tiff) compression algorithm written in vhdl. The design…

License : LGPL
Language : VHDL

Altera Cyclone III 3C120 Video Stream Scaler

The Video Stream Scaler scales streaming video up or down in resolution. Bilinear and nearest neighbor resize modes are supported. This core…

License : LGPL
Language : Verilog

Graphics Accelerator with Bresenham Line Drawing Algorithm

This project is a group of hardware units that perform graphics algorithms. For testing purposes, beside the Units that perform these algorithms,…

License : LGPL
Language : VHDL

16x2 LCD Display Module Using Verilog

There are a great many 16x2 LCD displays available to electronic design engineers. Nearly all of them are controlled by the Hitachi HD44780 control…

License : LGPL
Language : Verilog

FPGA Implementation JPEG Encoder Verilog

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a…

License : LGPL
Language : Verilog

Text Mode Monochrome Video Display Adapter for VGA monitors

This VHDL macro is a Text Mode Monochrome Video Display Adapter for VGA monitors. It can be used as a peripheral for a soft-processor, external…

License : LGPL
Language : VHDL

Memory Mapped LCD Controller (Samsung KS0073)

Simple memory mapped, character type dot matrix LCD controller for interfacing the Samsung's KS0073. The controller supports the 40SEG…

License : LGPL
Language : VHDL

LCD to HDMI Output Interface IP

This is an LCD to HDMI converter that is tested on NexusVideo board from DIGILENT. Is a generic IP that do not necesitate any setup, only take the…

License : LGPL
Language : Verilog

RTF Bitmap Multiple Display Controllers

Video frame buffer. This core is a low to medium resolution bitmap display controller. It was engineered for use on the Nexsys2 board, a Spartan3e…

License : LGPL
Language : Verilog

Digital PAL/NTSC Video encoder

Connecting to the world outside This part was completely redesigned due to variant output inpedances of different CPLD/FPGA and to reduce the…

License : LGPL
Language : VHDL

RTF Sprite Controller | Hardware Cursors

There is a new sprite controller which operates differently from the original. The original used image caches and supported a color depth up to 32k…

License : LGPL
Language : Verilog

All-in-One RTF Text Display Controller

An all-in-one text / bitmap / sprite controller (FT_VIC.v) is in the works. It will use a 640x400 video mode, fixed 80x50 char text display,…

License : LGPL
Language : Verilog

Video Dithering Using Sierra Lite Algorithm

The core supplies post-processing for a video signal. It reduces the color width while dithering the image to keep the impression of more colors…

License : LGPL
Language : VHDL

Demosaic (Bilinear)

Bilinear demosaicing is a digital image process used to reconstruct a full color image. With the demosaick algorithm it achieves reasonable image…

License : LGPL
Language : Verilog

Yet Another Verilog VGA

A simple VGA controller written in Verilog. I just add a pixel handler for simplicity.

License : LGPL
Language : Verilog