Silicon Labs Si533x Clock Buffers | New Product Brief
Silicon Labs Si53300 series of low-jitter fanout clock buffers can drive multiple clock output formats from any differential or single-ended input format.
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Silicon Labs Si533x Clock Buffers
Silicon Labs Si53300 series of low-jitter fanout clock buffers can drive multiple clock output formats from any differential or single-ended input format. The buffers offer up to 10 differential or 20 single-ended outputs at frequencies up to 1.25 GHz, with low additive jitter and low output-output skew. The buffers also offer glitchless clock switching, selectable drive strength to optimize jitter and EMI performance, a loss of signal indicators, and optional output clock division up to divide by four. Supported formats include LVPECL, low-power LVPECL, LVDS, CML, HCLS, and LVCMOS. Silicon Labs Si53300 series low-jitter fanout buffers have independent VDD and VDDO, providing integrated translation to and from 1.8 V, 2.5 V, and 3.3 V.
- Operating Frequency: DC to 1.25 GHz
- Outputs: 2-10 differential, 4-20 LVCMOS
- Additive Jitter: 45 fs rms (12 kHz to 20 MHz) typical
- Output-Output Skew: <50 ps
- Signal Formats: LVPECL, low-power LVPECL, LVDS, CML, HCLS, LVCMOS
- Independent VDD and VDDO: 1.8 V, 2.5 V, 3.3 V
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