Ahead of MWC 2023, AMD Unveils RF SoC Duo for 4G/5G Radio Unit Designs

Gearing up for next week’s Mobile World Congress—running February 27 to March 2 in Barcelona, Spain—AMD has this week announced a slew of details about what it will be showcasing at the event. Among this news, the company has launched two new members of its Zynq UltraScale+ RFSoC digital front-end (DFE) family.

 

The new additions to the Zynq UltraScale+ RFSoC digital front-end (DFE) family are aimed at 4G/5G radio unit designs.

 

The company says it expects these new RFSoCs are “right-sized” in terms of features to feed the expansion of deployment of 4G/5G radios into markets worldwide, specifically addressing designs where low cost, power- and spectrum-efficient radios are in demand for wireless infrastructure.

In this article, we examine the key details of the chips, look at some of the broader picture of AMD’s 5G technology, and share perspectives for the group pre-briefing with Giles Garcia, senior director at AMD’s AEGG Communications Group.

 

A Broad Sphere of 5G Involvement

In its press briefing, AMD put into context its extensive activity in 5G technology. Radio units are only one piece of that, says Garcia. Aside from radio units, the company also has technology in distributed units (DUs), central units (CUs, 5G core systems, and metro/transport converged access systems, he says.

“Today we have this technology portfolio deployed at six of the top seven 5G wireless equipment manufacturers,” says Garcia. This includes Cisco, Fujitsu, NEC, Nokia, and Samsung.

While each different segment of today’s communications landscape has different key system design challenges, Garcia says that, in the radio unit space, it’s all about efficiency. Today’s designs are focused on very large radio configurations, that are high capacity and complex.

 

“The KPIs (key performance indicators) that we are hearing as the challenges from the operators and wireless vendors are efficiently managed spectrums and power efficiency.”

 

AMD’s Roadmap for Radio Unit ICs

With those previously mentioned challenges in mind, AMD is announcing two new members of its RFSoC DFE (digital front end) family: the ZU64DR and the ZU63DR. For its part, the ZU64DR is targeted for GPP Split 8 radios designs.

Meanwhile, the ZU63DR is targeted for the low-end application of the radios in the 2T2R dual band, 4T4R, or small cell outdoor radios for power- and cost-effective, high volume applications.
 

AMD’s roadmap for 5G RU and O-RAN RU silicon. (Click image to enlarge)

 

As shown in the roadmap chart above, at the top is AMD’s beamforming technology for addressing mMIMO (massive MIMO) applications. The bottom row shows AMD’s RFSoC family. Its first member, a 16 nm device, went into production in 2018, while the current RFSoC DFE has been in full production since a year now, says Garcia.

Beyond what AMD announced this week and is covered in this article (in red above), the roadmap shows AMD’s Versal AI RF device that will double the capacity, and will address 5G advanced and 6G market applications, according to Garcia.

“Our two new RFSoC DFE devices are scheduled for production release in May 2023, meaning that we are accelerating the delivery of those devices because we are seeing a large market demand for those applications,” says Garcia.

 

Two New SoCs to Meet High RF Demand

Getting into the details of the two new chips, the Zynq UltraScale+ RFSoC ZU63DR specifically targets four transmit and four receive (4T4R) and dual band entry-level O-RAN radio unit (O-RU) applications. “For the ZU63DR, we integrated a new ADC, and we include the full DFE Hard IP,” says Garcia. “That means we are leveraging into the ZU63DR the complete DFE Hard IP that we have already in production on the ZU67DR.”

Meanwhile, the Zynq UltraScale+ RFSoC ZU64DR is targeted for eight transmit and eight receive (8T8R) O-RU applications using the 3rd Generation Partner Project (3GPP) split-8 option which supports alternative and legacy radio unit architectures.

Like the 63, the 64 device also embeds the ADC, and provides the DFE Hard IP, but without the Low-PHY block. “That’s because, for its target application, which is the Split 8 radios, the PHY functionality—High-PHY and Low-PHY—are both already handled by the systems’ distributed units,” says Garcia.

 

Details of each of the new RFSoC DFE family devices, compared with their in production counterparts

 

Explaining the differentiation for the new devices, Garcia says that it’s all about the DFE IP block and providing optimal performance. “These two devices are around 80% ASIC-based and 20% programmable logic,” he says.

That mix is essential to achieving the performance and efficiency demanded. “With that in mind, the two devices can address 400 MHz instantaneous bandwidth (IBW) and up to 280 MHz OBW (occupied bandwidth), so they are very performance efficient, capable devices,” says Garcia.

AMD says both RFSoC devices are expected to be in full production in Q2 of 2023. The company plans to showcase its Zynq UltraScale+ RFSoC DFE family at next week’s MWC Barcelona 2023, Hall 2, booth 2M61.