Cadence to Unveil New Design Solutions at TSMC 2016March 11, 2016 by Aaron LaBarbera
Cadence Design Systems will be dropping the curtain on some exciting new technology solutions this year at TSMC 2016 in San Jose on March 15th.
Cadence Design Systems will be dropping the curtain on some exciting new technology solutions this year at TSMC 2016 in San Jose.
Headlining these announcements are specifically those of new software supporting the design and implementation of 10nm FinFET and 16nm FinFET Plus chip sizes in the quest for ever-shrinking electronics and higher performance. Although other manufacturers like Samsung have announced months ago that they were offering 10nm silicon, there were issues with back-end resistance not improving as expected. It’s entirely possible that with the use of Cadence software that this will help sort out any issues without penalty to performance.
Another great unveiling will be that of their IoT sub system featuring Cadence SoundWire for MIPI®, QSPI, I2C, and SPI to reduce the effort required to integrate these technologies. The IoT is constantly seeing positive growth and Cadence’s announcements will just see it grow even further.
Virtuoso UltraSim post-layout verification, courtesy of Cadence.com (PDF)
The Virtuoso Multi-mode simulator with Spectre platform that will be demoed for show attendees’ promises industry leading design and verification simulation engines. The beauty of this system is in its numerous benefits to the designer in all phases of the design process. Just a few of these include: Silicon accurate modeling for the same device model equations across all simulators. Spectre APS, Spectre RF, and Spectre XPS simulation engines provide greater capacity and performance. Post-layout simulation for verification and optimization of large designs.
Spectre's RF Wireless Analysis and Visualization, courtesy of Cadence.com (PDF)
Another great tool debuting next week is the UltraSim Full-Chip Simulator. This software is designed to assist at the transistor level of hardware for a variety of SoC designs like digital, memories, and analog/mixed signal. Like the Virtuoso, Multi-mode the UltraSlim Simulator allows the designer pre and post verification of their designs.
The list of tools that Cadence Design Systems is showing off next week is quite extensive and quite frankly, too long to adequately list here. If you can’t attend TSMC 2016, checkout Cadence’s full offerings right here and their press release for more info.