DRAM, SRAM, FLASH, and a New Form of NVRAM: What’s the Difference?February 14, 2020 by Robin Mitchell
In this article, we will look at a proposed non-volatile DRAM and how it compares to current memory technologies.
DRAM is an essential component in computing technologies but it is not without its flaws. In this article, we will look at a new proposed memory—non-volatile DRAM—and how it compares to current memory technologies.
The Pros and Cons of Different Memory Technologies
When talking about computer performance, it is very easy to look at the CPU and make an assumption by its specification, including the number of cores, integrated specialized hardware (such as hyperthreading), and the number of caches that it contains.
However, external I/O is just as important as the CPU itself. This is why the fastest CPU on the market can be as slow as a 10-year-old CPU if both use the same external hardware. It's also why when upgrading a system, it is essential that the designer understands what is slowing down their system.
This is where the choice of RAM plays a vital role.
Although this article is by no means a comprehensive discussion of all the memory technologies out there, DRAM, SRAM, and FLASH can give us useful points of comparison when discussing the proposed memory technology.
While there is a wide range of different RAM types available (with varying speeds), they are almost always of one specific type: DRAM. DRAM (dynamic random-access memory) is a memory technology based on charging capacitors that is incredibly fast and cheap to implement. It also allows for high density.
But DRAM is not without its flaws.
A bit in DRAM can be stored as the presence or absence of charge on a capacitor.
DRAM is a volatile memory, which means it will lose the contents of its memory as the capacitors that store the bits discharge. The length of time this takes can vary, but usually, it will discharge within a few milliseconds. As a result, DRAM requires refresh cycles that read the data bits and then re-write the data back to the chip to re-enforce the stored data.
DRAM is also destructively read. This means that when a bit is read from DRAM, the contents of the memory bit that was accessed are forgotten and therefore require a write-back operation. These two problems mean that DRAM suffers in performance since it requires constant refreshing and re-writes to retain its data.
Another memory technology that exists, called SRAM, is a volatile memory technology that does not use capacitors to store bit. Instead, it includes a simple latch made of six transistors.
While SRAM also loses its stored information when turned off, it does not require refresh cycles because its feedback loop design latches data when it is written. This also means that reading data from an SRAM cell does not require a write-back operation to retain the data; this makes SRAM faster than DRAM.
SRAM cell. Image (modified) used courtesy of Encyclopædia Britannica
However, SRAM is far more expensive per bit since it requires six transistors, whereas DRAM requires a single transistor and capacitor. Because of this, SRAM is often found in a CPU cache where only a small amount of high-speed memory is required.
FLASH is a memory technology that is both similar to and distinct from DRAM.
First, each bit in FLASH memory is made up of a single transistor, but these transistors have a special layer called a floating gate. Bits are stored in FLASH memory by using quantum tunneling to trap electrons in the floating gate layer, which makes the transistor more or less conductive.
When a voltage is applied across the transistor bit, the conductive capability of that transistor will depend on whether there are electrons trapped in the floating gate.
Unlike DRAM, FLASH memory is non-volatile, which means that FLASH memory will retain any data stored to it when turned off. However, while FLASH memory can be quick to access and has a relatively low cost per bit, it has two problems that make it unusable as a CPU RAM.
Flash cell. Image used courtesy of Cyferz [Creative Commons Attribution 2.5 Generic]
The first problem is that NAND FLASH uses a memory topology where individual bits cannot be erased on their own. They instead require the erasure of a whole block of memory (changing individual bits requires a large erase/write cycle).
The second problem is that FLASH memory is physically destructive. The reason for this is that when a FLASH bit is erased, a large potential voltage (approximately 20 V) is required to remove the electrons trapped in a floating gate. This causes a small amount of breakdown in the oxide layer and over many write cycles, this will eventually destroy the bit.
Such transistors can be expected to survive as many as 100,000 erase cycles, which is not a problem for removable storage (such as a USB stick), but is unacceptable for use in DRAM.
The New Proposal
The problems with FLASH and DRAM may have been solved with a new proposed memory technology that offers to combine the benefits of DRAM with the benefits of FLASH.
A recent paper published by IEEE and authored by Dominic Lane and Manus Hayne at the Department of Physics at Lancaster University explains how the new memory technology works in a very similar method to FLASH.
Electrons are stored on a floating gate to retain information. However, the proposed memory bits have a triple AlSb/InAs layer that produces multiple quantum wells and is thick enough to ensure longevity or store information. The triple well configuration also has lower voltage requirements for writing and erasing.
Schematic of the proposed NVRAM's architecture. Image used courtesy of Dominic Lane and Manus Hayne
The use of multiple stacked conductive bands differs from traditional FLASH memory since FLASH memory relies on the oxide layer for insulating the trapped electrons.
The new proposed memory uses alternating semiconductor barriers. The alternating bands produce conductive bands that successively hold larger electron energies, making reverse tunneling of electrons from the floating gate virtually impossible (hence producing non-volatility).
However, the article does not clearly state why the new design requires a considerably lower write/erase voltage (being less than 2.3 V). Further reading suggests that the use of multiple barriers that are closer together reduces the voltage needed for electrons to tunnel across the gap.
The reduced voltage significantly reduces damage done to layers. As electrons are tunneled into the conduction layers, they increase the resistance against electrons trying to tunnel back out. The use of multiple conduction bands (which have different energy band gaps) means that electrons must have specific energy to be able to tunnel into those regions.
Therefore, all the electrons trapped in a specific well will have similar energies. That energy, however, will not allow for the electron to tunnel into a neighboring band, thereby trapping it.
The new memory model shows promise as a new memory technology for several reasons. The memory is non-volatile, meaning that it retains its data even when switched off. But this also means that there is no need for refresh cycles, which can dramatically improve performance.
The new memory system is capable of operating at similar speeds to DRAM access times—a critical feature if it is to replace DRAM.
The new memory proposal also uses significantly less energy because of the lower gate voltages required. Therefore, it will dissipate less heat per bit. But until a semiconductor producer can take this design and put it onto silicon, we will have to be content with good old-fashioned DRAM.
What questions do you have about memory technologies? Leave your thoughts in the comments below.