Advances in semiconductor devices have consistently been improving our technological limits by reducing device proportions for the past few decades. The current graphene and silicon chips have nearly reached optimization. Due to their technological and scientific limitations, we have been forced to explore new and better material alternatives.
Over 20 years ago it was suggested that carbon nanotubes would be the answer to creating chips with smaller dimensions due to their electrical conductivity. However, this idea had been tossed aside for decades due to the discrepancies and deviations that arose between metallic and semiconducting single-walled carbon nanotubes in addition to problems concerning wafer alignment.
Rendering of a single-walled carbon nanotube. Image sourced from Wikimedia Commons.
UW-Madison's CNT Transistor
The team was led by two professors of materials and engineering Padma Gopalan and Michael Arnold. The UW-Madison team was able to produce a transistor with a current 1.9 times quicker than current silicon transistors. The speed at which a current can transit from a transistor’s source and drain terminals regulates the speed at which a circuit can operate. Faster currents enable devices in circuits to be charged faster.
In their research published in the journal Science Advances the team explains the difficulties and production processes involved in creating the new CNT transistors. The team was able to pinpoint distinguishing processes that enable specific polymers to sort the single-walled carbon nanotubes to produce an immaculately pure solution.
Specific conditions were established that enabled the removal of nearly all (to .01%) of the metallic. A process called floating evaporative self-assembly (or FESA) was developed by the team back in 2014 and was used to deposit arrays of aligned semiconducting single-walled carbon nanotubes at high deposition velocity with exemplary control of placement and quantity.
As of now, the team has been able to manufacture this process on a 1x1 inch scaled wafer.
Image courtesy of the University of Wisconsin-Madison.
The UW-Madison team benchmarked the performance of their CNT arrays compared to state-of-the-art single CNT FETs and to commercial metal oxide silicon FETs with the same geometry, size, and leakage current. The result is that the CNT arrays produced current 1.9 times higher than the oxide silicon MOSFETs.
Using the data from single CNT assessment, the researchers hypothesized that the new transistor will be capable of functioning five times faster with potential to become five times more efficient than current silicon transistors.
The layout of a typical MOSFET. Image courtesy of Oxford University.
The Future of Transistor Technology
The advancements in their research could potentially lead the CNT transistors to succeed the use of silicon transistors while continuing to abide by the old notion of Moore's Law. These transistors are particularly useful in wireless communication and computer chips among various other fields as they demand large current flows through their circuitry, which is exactly what the new CNT transistors provide.
The team is still continuing their research, currently adapting the size and shape of the CNTs to match their silicon counterparts, which change geometry regularly. They are also in the midst of developing RF amplifiers to boost signal strength.
The CNT technology is approaching the level of development where research will be aimed at advancing the performance in potential devices. The work is currently patented and is receiving funding from the NSF and several military branches.
Michael Arnold has been quoted as saying that this is “a critical advance toward exploiting carbon nanotubes in logic, high-speed communications, and other semiconductor electronics technologies.” According to him, CNTs finally outpacing silicon has been a major goal for nanotechnology for 20 years.
To learn more, check out this video of the researchers going over their invention: