IBM Up Against Moore’s Law with 5nm Chip
Moore’s Law will be relevant for a few more years with recent news that IBM, GlobalFoundries, and Samsung has succeeded in fitting 30 billion transistors onto a single, 5nm chip.
Moore’s Law will be relevant for a few more years with recent news that IBM, GlobalFoundries, and Samsung succeeded in fitting 30 billion transistors onto a single, 5nm chip.
With concerns that the trend Moore's Law predicted, which states that the number of transistors able to fit on a single chip would double every two years, was slowing down or becoming obsolete, research into High Performance and Parallel Computing has begun to gain traction as one of the solutions for ensuring that computation power continues to expand, while decreasing power and resource requirements.
IBM managed this feat by using a new type of gate: the Gate All Around Field-Effect Transistor (GAAFET). This is similar to transistors found in 7nm chips, which are Fin Field-Effect Transistors (FINFET). Both are “3-dimensional”, extending a fin upward to allow for more silicon, but in the case of GAAFET, there are three nanosheet layers of silicon.
Manufacturing chips this small is a complicated task. However, by using ultraviolet laser etching the process becomes more precise and manageable, which is part of the breakthrough allowing IBM to create 5nm chips.
Tech industry analysts in the past did not predict a 5nm chip would be possible before the early 2020s. While IBM and its partners still have some time to go before they are likely to begin producing the 5nm chip, it is still a head start in the industry.
Currently, 10nm is the smallest chip available on the market, with smartphones typically utilizing 14nm Qualcomm chips. The 5nm chip is promised to be significantly faster and power efficient (up to 40 and 75 percent more efficient, respectively) compared to its 10nm predecessor; IBM believes days could be added to the battery life of phones.
There has been speculation that the GAAFET could be scaled down to as small as 3nm. However, the more a chip is scaled down, the higher the potential for problems with physical limitations of transistors that small, including added complexity in manufacturing.
GAAFET with three nanosheet layers. Image courtesy of IBM.
10nm and 14nm Production and Performance
Talking about 3nm chips may be getting ahead of ourselves, since 7nm chips have yet to enter the market, and 10nm chips have just begun to appear.
Samsung only started manufacturing 10nm chips last October, which were reported to have a 27 percent increase in performance and a 40 percent increase in power efficiency compared to 14nm chips.
Coffee Lake, Intel’s codename for its 8th-generation Core processors, is the successor of the Kaby Lake 14nm microarchitecture. Reportedly, it refines the manufacturing process with up to a 30% increase in performance compared to Kaby Lake. The recently announced Intel i9 chip will also utilize a 14nm chip.
However, Intel claims that chip size is not the best way to describe the actual improvements of a chip’s density and that Samsung’s 10nm chips are still equivalent to Intel’s 14nm chip before its refinement. An alternative method of addressing performance involves the use of a formula which focuses on standard logic cell density and weighted based on typical chip design.
I wonder what the reliability of these will be. Let’s stick them in self driving cars to find out!
“30 billion transistors onto a single, 5nm chip.” , sorry but this is his wrong. The transistor technology size is 5nm. It’s against the laws of physics as we know it to have 30 billion transistors on a chip with a size of 5nm