Infineon Achieves 800 MB/s Data Throughput with HYPERRAM 3.0

August 16, 2022 by Jeff Child

Upping the game for low pin count, high throughout DRAM, Infineon’s third generation HYPERRAM device doubles bandwidth to 800 MB/s in a 49-pin BGA.

Targeting what the company says is an underserved spot in the dynamic random-access memory (DRAM) market, Infineon Technologies has unveiled its HYPERRAM 3.0 DRAMs. Featured on the device is a new,16-bit extended version of the HyperBus interface that doubles throughput to 800 MB/s.

In this article, we examine the details of the new memory chip, we discuss the application niche the device is designed to serve, and we share insights and analysis from our interview with Bobby John, senior manager at Infineon Technologies’ RAM Business Unit.


HyperBus Enables High-throughput, Low Pin-count

The HYPERRAM 3.0 device improves on Infineon’s second generation of the family of devices introduced in 2021. HYPERRAM devices use the company’s HyperBus interface that enables the devices to offer higher bandwidth compared to traditional parallel expansion memories.


By using an extended 16-bit version of the HyperBus interface, HYPERRAM 3.0 doubles throughput compared to the 2.0 version.

By using an extended 16-bit version of the HyperBus interface, HYPERRAM 3.0 doubles throughput compared to the 2.0 version. (Click on the image to enlarge)


Originating from Cypress Semiconductor, which Infineon acquired in 2020, HYPERRAM is a stand-alone PSRAM (pseudostatic RAM)-based volatile memory. It was designed to provide a simple and cost-optimized way to add extension memory. While its data rates are comparable to SDR (single data rate) DRAM, HYPERRAM offers much lower pin-count and lower power consumption.

According to Infineon, the boost in per-pin data throughput enabled by the HyperBus interface lets engineers use microcontrollers with fewer pins and PCBs with fewer layers. The original HyperBus interface uses a high-speed 8-bit DDR interface for both address and data. It also provides a differential clock, a read/write latch signal, and a chip select. The HyperBus interface is JEDEC compliant.

HYPERRAM 3.0 uses a new 16-bit extended version of the HyperBus called Hyberbus Extended I/O. This enables HYPERRAM 3.0 to offer 800 MB/s throughput, which is twice the 400 MB/s of its 2.0 predecessor. Available in 245 Mb densities, HYPERRAM 3.0’s 49-pin FBGA package is a bit larger than 2.0’s 24-pin FBGA but still much smaller than typical parallel bus SDRAMs.

Like the 2.0 version, the new 3.0 flavor supports industrial and automotive temperature grades, but 3.0 only goes up to automotive grade AEC-Q100 Grade 2: -40°C to +105°C whereas HYPERRAM 2.0 supports Grade 1 at -40°C to +125°C. More information is available in the HYPERRAM 2.0/3.0 product brief.


Comparison: HYPERRAM 3. vs. Alternatives

For many applications, the traditional DDR DRAM designed for PCs, servers, and data centers is not well suited to serve as expansion memory. HYPERRAM 3.0 blends low pin count and low power to fit the needs of a variety of systems. These include video buffering, factory automation, Artificial Intelligence of Things (AIoT), and automotive vehicle-to-everything (V2X). The technology is also a good fit for applications requiring scratch-pad memory for intense mathematical calculations, says Infineon.

According to Infineon, other low pin count alternatives on the market include ADMUX (address data multiplexed) PSRAM and the SDR SDRAM—each is a popular choice in the 64 Mb to 512 Mb expansion memory space. Infineon’s Bobby John says a comparison of those technologies with HYPERRAM is particularly vivid when it comes to packaging size—an 82% smaller size comparing the 48 mm2 24-ball FPGA package to an SDR SDRAM’s 54-pin TSOP.


Compared to other memory expansion technologies, HYPERRAM 2.0/3.0 offers smaller packing, fewer data transfer pins, lower power, and higher throughput. (Click the image to enlarge)


A significant amount of pin reduction comes from the fact that HYPERRAM uses fewer pins for data transfer. HYPERRAM needs only 12 pins for the 2.0 version, compared to the 31 pins required by AUMUX PSRAM. “In HYPERRAM Gen 3 we’re still able to achieve much higher throughput while only increasing to 21 pins,” says John. “That’s still much better than the alternative memory technologies.”

From a current consumption perspective, HYPERRAM again has the advantage thanks mostly to its PSRAM technology. HYPERRAM’s 25 mA maximum active current puts it up to 85% lower than SDR DRAM’s power specs. Such levels of low power are critical in consumer applications such as wearables or smart home devices based on batteries, says John.

Throughput is where the difference shown by HYPERRAM 3.0 is the most dramatic. “From a throughput perspective, we beat the traditional memory alternatives pretty well at 400 MB/s for our 2.0 and 800 MB/s on our 3.0 products,” says John.


Positioned for High Throughput, Low Pin Count

In summary, the value proposition that HYPERRAM provides for engineers is its ability to achieve very high data throughput via a low count interface. The graph below puts that into perspective.


HYPERRAM 2.0 and 3.0 devices can offer high throughput rates while maintaining lower pin counts compared to alternative memory technologies.

HYPERRAM 2.0 and 3.0 devices can offer high throughput rates while maintaining lower pin counts compared to alternative memory technologies.


The graph above shows the throughput that you get from a device versus the number of pins that are required for data transfer. “If you look at all the traditional memories—SDR DRAMs, ADMUX PSRAM and DDR memories—they all achieve throughputs with a much higher number of pins,” says John.


You might require up to 30- to 40-pins to achieve this level of throughput. But HYPERRAM just uses 12 pins-or 21-pins and you are still able to match the performance of the other technologies. This is the area that HYPERRAM is servicing: Low pin count, high performance embedded devices. 


Serving the Needs of Embedded Systems

The history of DRAM devices is tightly linked to mainstream, high-volume applications such as PCs and servers. Throughout decades of DRAM evolution, these memory chips have synched up with the needs of these mainstream computing systems.

Because embedded systems—like industrial control, automotive, and IoT—have different memory needs than traditional computing, alternative technologies have emerged over the years. HYPERRAM perhaps exemplifies a further leap in those efforts and shows that engineers don’t need to trade off performance in low pin count implementations.



All images used courtesy of Infineon Technologies

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