Achieving Magnetic Tunnel Junctions With Record High Speeds for MRAM Peak Efficiency

June 28, 2020 by Luke James

A group of researchers at Japan’s Tohoku University have announced the development of a magnetic tunnel junction with some of the highest speeds seen yet.

Tunnel magnetoresistance is a magnetoresistive effect that occurs in a magnetic tunnel junction (MTJ). Most notably, it forms the basis for non-volatile magnetoresistive random-access memory (MRAM) but it also has applications in non-contact sensing applications with TMR sensors. 

Now, a Japanese research team from Tokyo University, led by Professor Tetsuo Endoh, has announced their development of an MTJ with a 10 ns high-speed write operation, sufficient endurance (>1011), and with highly reliable data retention over 10 years at 1X nm size. Achieving a 1X nm spin-transfer torque-magnetoresistive random access memory (STT-MRAM) and non-volatile logic (NVL) has wide-reaching applications. 


Essential Components in Processors

As they offer low power consumption, STT-MRAM, and NVL with MTJ and CMOS hybrid technology are essential components found in semiconductor memory and logic such as computer processors. 

To put spintronics technology to good use, higher speed write operation, greater endurance, and even lower power consumption are required. Additionally, higher operation temperatures, better scalability, and data retention in the long-term (> 10 years) are also needed. However, researchers have faced significant problems with data retention, often achieved at the expense of operational performance such as write speed. To date, this has limited the potential of STT-MRAM and NVL. 


A schematic and TEM image of the developed quad-interface MTJ structure.

(a) A schematic and (b) TEM (transmission electron microscopy) image of the developed quad-interface MTJ structure. Image credited to Tohoku University


Developing a New MTJ Stack Design

To facilitate the application of 1X nm node STT-MRAM and NVL to a wide range of applications, the research team developed a new MTJ stack design and fabrication technology for Quad interface type iPMA-MTJ (Quad-MTJ). 

Using these new technologies, the team successfully fabricated advanced Quad-MTJ. They have now been able to show that the current write density of Quad-MTJ can be reduced by over 20% at a 10 ns high-speed write operation in contrast with the conventional Double-MTJ.

This is the case even though the thermal stability factor of Quad-MTJ is two times larger than Double-MTJ. In simpler terms, the data retention of Quad-MTJ can be maintained for over 10 years and at a higher operating temperature than Double-MTJ. Quad-MTJ also achieved endurance levels of over 1011. 


Suitable for Key Electronics Applications

According to the research team, Quad-MTJ technology, and 1X nm STT-MRAM and NV-Logic with MTJ/CMOS hybrid technology will open up a new spintronics base LSI that is suitable for a wide range of applications. These range from the low-end (IoT systems and sensor networks) to the high-end (AI systems and image processing) of the spectrum.