“Extend Beyond Moore’s Law”: Xperi Unveils New Semiconductor Wafer Bonding Technology

May 27, 2019 by Gary Elinoff

Watch out, Moore's Law. Growing demands on memory have pushed semiconductor companies to pack more onto chips.

Watch out, Moore's Law. Growing demands on memory have pushed semiconductor companies to pack more onto chips.

Xperi Corporation has announced a new IC package bonding technology for semiconductor devices which they've named DBI Ultra.

DBI Ultra is the successor to Invensas’s DBI wafer-to-wafer hybrid bonding, which has been widely employed in the production of smartphone image sensors. DBI stands for direct bond interconnect, an apt name for a method that directly places two layers of semiconductor wafers together "at room temperature without any pressure or adhesives" between them. According to Invensas, DBI has been impactful for various applications, including mobile devices, IoT devices, and various uses for industrial, automotive, and medical industries.

The updated technology, DBI Ultra, is poised for similar success in 3D stacked memory, as well as in 2.5D and 3D applications requiring the integration of memory with CPUs, GPUs, FPGAs, or SoCs. 

2.5D vs. 3D IC: Allowing Next-Gen Integrated Circuits

You may have seen the terminology for a "3D IC" before, probably in contrast to a 2D integrated circuit. But how about 2.5D?

In a 2.5D structure, dies are not stacked on top of or below other dies. Rather, the dies are packaged on a single plane and interconnected to each other.

With 3D structure, as enabled by processes like DBI Ultra, the dies are stacked one on top of each other in multiple layers. Thus, a true three-dimensional topology is made possible.

Instead of cramming more devices into a given length-and-width space, with 3D integration, engineers can build upward, in the third dimension. The obvious analogy is instead of cramming more apartments into a ground-floor building plot, a second floor is built, and a third floor on top of that, and so on. Each subsequent floor can house as many tenants, in the form of electronic devices, as the original first floor can.

The “stairways” electrically connecting the “floors” to each other are called TSV’s (through-silicon vias). The short length of the TSVs make for a fasters electrical pathways between the dies, essential for the ultra-fast bandwidths that the electronic devices of today and tomorrow will require.


IDBI wafer-to-wafer hybrid bonding connects two silicon wafers. Image from Invensas


Craig Mitchell, President of Invensas calls DBI Ultra "the ultimate 3D interconnect and integration solution.” He goes on to claim “this production-worthy die-to-wafer hybrid bonding platform allows the semiconductor industry to extend beyond Moore's Law providing unprecedented 2.5D and 3D integration flexibility required for next generation electronics."

It's worth mentioning that Moore's Law technically refers to the density of transistors on a chip. Perhaps it's most accurate to say that Xperi is here avoiding the typical issues that come with challenging Moore's Law by adding more layers to a chip rather than the traditional method of packing more transistors into an IC.

What Are High Bandwidth Memory Stacks?

HBM stands for high bandwidth memory. Stacks of this dense memory are built of vertically stacked dies. Vertical stacking means shorter electrical pathways, which enables faster memory speeds.

3D memory has been a hot topic for years, including HMC (hybrid memory cube) work from Micron in 2016 and others today, including Promwad. 3D flash memory, in particular, has been pursued by Samsung, SK Hynix Semiconductor, and Yangste Memory Technologies company. Toshiba's memory unit has been making waves in this space, as well, introducing the BiCS 3D flash memory method of stacking die for denser memory (96 layers, last we checked).

Produced by Xperi’s Invensas subsidiary, DBI Ultra will make it possible to manufacture 12- and 16-high HBM stacks, an important advancement given the demanding packaging height and performance requirements for next-generation, high-performance computing.

The latest JEDEC standard only specifies 12-high HBM stacks, so Xperi’s ability to reach up to 16-high with DBI Ultra is noteworthy.


Wafer-to-wafer, die-to-wafer, and die-to-die bonding. Image from Invensas


DBI Ultra enables room-temperature hybrid bonding to allow for densely-packed memory applications in particular. It forgoes traditional copper pillars and underfill, which allows for much thinner stacks that are still able to accomplish fine interconnects, down to 1 um interconnect pitch.

DBI Ultra will be showcased at Xperi’s booth at the IEEE Electronic Component Technology Conference (ECTC) 2019 this week in Las Vegas, NV (May 29th and 30th).

Around the Industry

Two of the most pressing demands in electronic design are the need to process information faster and the need to use less power doing it. Both of these ends are furthered through die-to-wafer and die-to-die bonding. Not surprisingly, there is much interest around the industry in this technology.

  • Samsung’s Flashbolt offers a 410 gigabytes-per-second (GBps) data bandwidth and 16GB of memory. It is aimed at applications in supercomputers, graphics systems, and AI. Various sources report that it is built in an 8-Hi stack configuration.
  • AMD is also among those actively embracing HBM memory because of power and speed limitations imposed by present-day mainstream technologies.


HBM memory. Image from AMD



Do you have expertise in wafer-to-wafer bonding? Is it something you'd like to learn more about? Let us know in the comments.