Renesas Combines Synchronous Buck and LDO Regulator In One Rad-hard ICJanuary 31, 2020 by Gary Elinoff
The ISL70005SEH, geared for satellite orbit, incorporates both a synchronous buck converter and a low dropout (LDO) regulator in one monolithic IC.
Renesas has announced ISL70005SEH, a device the company is calling "industry’s first single-chip synchronous buck and low dropout (LDO) regulator targeting low-power FPGAs, DDR memory and other digital loads."
The point-of-load (POL) power solution aims to free up board space and weight capacity for spaceflight payload applications.
The unit is said to enable satellite developers to reduce the size, weight, and power (SWaP) requirements for units geared for medium Earth orbit (MEO) and geosynchronous Earth orbit (GEO).
The ISL70005SEH. Image used courtesy of Renesas
The radiation-hardened device is designated for systems with 3.3 V or 5 V power buses. The LDO regulator features a 75 mV dropout voltage and can source up to ±1 A. Renesas claims the buck regulator is 95% efficient and can supply a continuous load of 3 A.
Using an external resister, ISL70005SEH's switching frequency can be adjusted to range from 100 kHz to 1 MHz, allowing a smaller filter size.
Passing Tests to Endure Harsh Conditions
Wafer Acceptance Testing. The space-grade ISL70005SEH is wafer acceptance tested over a high dose rate (HDR) to 100 krad(Si). It is also tested over low-dose-rate (LDR) for enhanced low-dose-rate sensitivity (ELDRS) up to 75 krad(Si).
Single Events Testing (SEE). At a linear energy transfer (LET) of 86 MeV∗cm2/mg, SEE testing has uncovered no single event burnout (SEB) or single event latch-up (SEL).
Although built on the same wafer, the buck regulator and the LDO are independent of each other.
Block diagram of the ISL70005SEH. Image used courtesy of Renesas
Both the buck and LDO “subsystems” feature output undervoltage and overvoltage detection and output overcurrent protection. The device also includes protection against over-temperature and input undervoltage lockout (UVLO).
The ISL70005SEH offers programmable soft-start and enables functions along with power-good indicators for both the buck and the LDO. This important feature makes the task of supply rail sequencing simpler for the designer.
The buck regulator’s power stage integrates two synchronous operation MOSFETs. The high-side and low-side MOSFETs are PMOS and NMOS devices, respectively. The MOSFETs are optimized for low RDS(ON) for efficient use of power over the 3 A operating range.
The LDO employs separate voltage regulation feedback loops for sourcing and sinking current. A dead-band voltage region disables the LDO output during a sourcing/sinking transition to prevent internal shoot-through. Both of the LDO’s sourcing and sinking NMOS FETs are disabled during this interval.
To Space It Goes
Renesas has stated the ISL70005SEH's usefulness in distributed power systems of spaceborne payloads and VDDQ/VTT rails for DDR memory. The device might also help with point-of-load power for auxiliary and I/O supply voltages and for low-power FPGA cores.
The left side of the below image illustrates a power solution based on the ISL70005SEH for DDR memory. The right side illustrates LDO load regulation.
ISL70005SEH for DDR2 memory (left) and LDO load regulation, DDR2 configuration (right). Image (modified) used courtesy of Renesas
“The ISL70005SEH gives satellite manufacturers the superior radiation performance and SWaP and BOM savings they want,” said Philip Chesley, VP of the industrial and communications business division at Renesas.
“Our dual output POL regulator also provides the configurability to address multiple applications in commercial telecommunication satellites, military Satcom satellites, and science and exploration missions.”
The ISL70005SEH is available in 28 Ld ceramic dual flat-pack package with dimensions of 18.8 mm by 13.97 mm. The unit is also supplied in die form.
The device can operate the full -55°C to +125°C military temperature range.
The ISL70005SEHEV2Z evaluation board. Image used courtesy of Renesas
The evaluation board is optimized for 3 V to 5.5 V inputs and generates a 3 A. The board also includes a 1.8 V to 3.3 V buck output and a 1 A ±1.2V LDO output. It is configured for DDR memory VDDQ and VTT supply rail applications.
Preserving board space matters in most applications, but this is especially important for ICs headed to space. What are your top design tips for saving board real estate in aerospace and defense applications? Share your ideas in the comments below.