Semidynamics Provides All-In-One AI IP to Facilitate AI Chip Design

April 11, 2024 by Jake Hertz

The All-In-One AI IP bundles a CPU, GPU, NPU—and Semidynamics' unique, in-house "Gazzillion Misses" technology—into a single subsystem.

The AI chip design field is full of players, ranging from industry giants like Nvidia to smaller and lesser-known startups across the world. One such startup is Semidynamics, a European company specializing in custom RISC-V core AI technologies.

Recently, Semidynamics announced its new All-In-One AI IP solution for AI chip design. Let’s take a look at the company’s new offering and its in-house Gazzillion Misses technology underlying it. 


Semidynamic Bundles AI Essentials Into One Package

AI chip architectures have traditionally relied on multiple IP blocks, such as GPUs and NPUs, alongside the system CPU, each tasked with specific functions to meet the escalating computational demands of AI applications. This approach, however, leads to significant inefficiencies: high latency from transferring data between blocks, complex programming from disparate instruction sets and toolchains, and obsolescence risks as AI algorithms evolve rapidly.


Traditional AI SoC architectures are distributed

Traditional AI SoC architectures are distributed. 

Semidynamics' All-In-One AI IP contrasts this approach by integrating RISC-V, vector, tensor, and its in-house "Gazzillion Misses" technology into a single unified processing element. This IP eliminates the need for multiple IP vendors and toolchains, thereby simplifying programming to a single RISC-V instruction set and development environment. Semidynamics' configuration also streamlines data processing with minimal cache misses and zero communication latency between processing units. The company claims its unified architecture, therefore, optimizes power, performance, and area (PPA) while significantly enhancing the chip's adaptability to new AI algorithms.


All-in-One AI IP

The All-in-One AI IP fuses CPU, GPU, and NPU into one subsystem. 

The All-In-One AI IP is adaptable and scalable to address to the dynamic demands of AI applications, from modest to extremely high computational requirements, without the risk of becoming outdated. This approach has the potential to democratize access to powerful AI chips, catering to both current and yet-to-be-conceived AI algorithms.


Semidynamics’ Gazzillion Misses Technology

While many designers might expect CPUs, GPUs, and NPUs in an AI hardware discussion, Semidynamics claims it stands apart from the rest with its unique Gazzillion Misses technology.

Traditional processors can sometimes encounter a cache miss, where the CPU doesn't find the data it needs in the cache and has to fetch it instead from the main memory. Cache misses can cause the processor to enter a "stop-and-go" mode and idle the CPU for numerous clock cycles while it waits for the memory access to complete. Typically, processors can only handle a few of these events before they stall and take a hit on efficiency and performance.


A traditional processor can be stalled by cache misses

A traditional processor can be stalled by cache misses. 

In contrast, Gazzillion Misses allows a processor to issue up to 128 simultaneous memory requests. This capacity dramatically reduces the processor's idle time to almost zero since it can continue performing useful processing while the memory system is serving the previous misses. By effectively hiding memory latency, Gazzillion Misses technology ensures that the processor can sustain high-bandwidth memory systems without stalling, even with long latency data access.

The technology is particularly adept in data center machine learning contexts, where handling highly sparse data efficiently is crucial. The Gazzillion Misses technology enables SoCs to deliver such data to the compute engines without requiring a large silicon investment, optimizing performance and reducing costs.


Semidynamics core with Gazzillion Misses technology

Semidynamics core with Gazzillion Misses technology.

Gazzillion Misses can fundamentally transform how systems handle large data loads and access memory, maintaining high throughput and efficiency. This technology is integral to Semidynamics' vision of providing fully customizable RISC-V processor IP that can adapt to a project's specific requirements, including proprietary features, within a very short time frame.


New Tools for RISC-V

Semidynamics says its new IP can help RISC-V designers achieve greater performance and scalability in their systems. With architectural features like Gazzillion Misses technology and a highly integrated processing subsystem, Semidynamics’ All-In-One AI IP may be a useful solution for designers in the AI computing space.



All images used courtesy of Semidynamics.