Sarah L. Harris Associate Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas

Understanding RISC-V Architecture and Implementation on an FPGA

Join Digi-Key for a close look at the inner workings of the RISC-V processor core and ways to implement a soft RISC-V processor core in a target (Xilinx) FPGA device. The RVfpga webinar covers the foundational knowledge that the next generation of Programmers and Engineers need to harness the potential of RISC-V. Digi-Key is proud to sponsor this webinar in collaboration with Imagination Technologies featuring Prof. Sarah Harris (UNLV). The webinar attendee will learn how to:

  • Target a commercial RISC-V core and system-on-chip (SoC) to an FPGA
  • Program the RISC-V SoC
  • Add more functionality to the RISC-V SoC
  • Analyze and modify the RISC-V core and memory hierarchy

After completing the RVfpga webinar, attendees will walk away with a solid understanding of a commercial RISC-V processor, SoC, and ecosystem.

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