LDRA Updates Tools to Automate Worst-Case Execution Time Analysis for RISC-V
The tool suite automatically analyzes shared memory and measures worst-case execution time to ensure deterministic execution time for RISC-V processors.
Rain AI Tapes-Out Low Power AI Accelerator Chip with Synopsys Cloud and IP in Under a Year
Read this success story and learn how Rain AI selected Synopsys Cloud SaaS design platform providing end-to-end EDA and IP solutions.
Innovating AI Hardware with Cloud Solutions
Synopsys Cloud offered one-stop-shop for complete EDA, IP and infrastructure needs.
Broadcom Unveils 200G Per Lane DSP PHYs to Bolster AI Infrastructure
While one of the new DSP PHYs reportedly offers the industry’s lowest power consumption for 800G, the other is the first 200G/lane DSP with integrated VCSEL drivers.
Partnerships Abound to Assist Engineers Working With 5G and 6G
These collaborations are shaping the future of wireless networks, from RF power consumption to AI-driven data compression.
Microchip Packs Analog Peripherals Into 32-bit MCU Family
Announced at Embedded World, the PIC32A MCUs integrate high-speed analog peripherals and safety features for consumer electronics or automotive OEMs.
Crypto Quantique Simplifies CRA Compliance for Embedded Security
Crypto Quantique is helping embedded designers comply with the European Cyber Resilience Act by automating essential security functions and integrating…
How RISC-V Enables Shift-Left Practices for Securing Embedded Systems
RISC-V’s open architecture enables a shift-left approach to security in embedded systems. Learn how it smooths the way for integrating security features and…