Optimizing Power Management with NXP’s i.MX RT500 Crossover MCU

A key consideration for MCU designers is how power is managed and distributed. Without consideration of CPU clocks, memory, and peripherals, designers might find themselves unable to make the transition from a design to an actual, physical product. 

This article provides an introduction to microcontroller power management concepts. This will include discussion of MCU power modes and how they affect the operation of the device, how much current the part draws in each mode, and how long it takes the MCU to wake up from a low-power mode. We will also investigate how the MCU’s I/O pins and SRAM configuration influence the overall power consumption of the device. The NXP i.MX RT500 family of crossover MCUs will be used to provide examples of how these power management concepts can be employed by embedded developers in their applications. The i.MX RT500 MCU provides power control and power management functionalities that allow the device to operate with as little power as possible.

 

An Overview of the i.MX RT500 Crossover MCU

i.MX RT500 is a family of dual-core microcontrollers based on a powerful Arm® Cortex®-M33 core with a clock speed of up to 200 MHz. The i.MX RT500 series offers rich protection features such as Arm TrustZone® and a built-in memory protection unit (MPU) that supports eight regions. The CASPER crypto co-processor enables hardware acceleration to boost various functions required for asymmetric cryptographic algorithms. The PowerQuad hardware accelerator is another efficient co-processor of the i.MX RT500 crossover MCU, and it aids the main CPU in performing DSP calculations. The i.MX RT500 is suitable for secure and low-power embedded HMI applications, IoT devices, hearables, and smart consumer devices because of its additional highly optimized Cadence® Tensilica® Fusion F1 audio DSP, a dedicated 2D GPU with vector graphics acceleration, and various display interfaces.

 

Figure 1. i.MX RT500 MCUs are fit for powering modern embedded HMI applications that require fast and visually pleasing graphics and user interfaces. Image courtesy of NXP.

 

Complex mixed-signal MCUs often contain multiple power supplies on-chip to both improve power control and reduce power supply noise cross-talk. For power control, the core can run at lower voltage than the I/Os. In addition, unused sections of a MCU can be powered down when not in use. For noise rejection, the noisy power supplies that feed the I/O and digital logic can be isolated from the on-chip analog functions.

As an example of using separate power rails, the i.MX RT500 family of MCUs have four independent power rails that supply different parts of the internal circuitry:

1. The V_DDCORE rail powers the chip’s main logic, DSP, peripherals, and memory. This supply rail is adjustable between 0.6 V and 1.1 V, and engineers are free to use the device’s internal PMU (power management unit) or utilize an external PMIC (power management IC). The required voltage depends on the core clock frequency before the CPU clock divider.
2. V_DD1V8 is a 1.8 V supply that drives on-chip analog functions other than the ADC and comparator. This rail also supplies the built-in PMC module, including bandgap, POR, temperature sensor, and core low-voltage and high-voltage detection. The V_{DD1V8_1} line supplies power to the on-chip digital logic.
3. The V_{DD_AO1V8} rail provides power to parts of the device that are always on, such as the RTC, RTC wake-up timer, always-on POR, and the RESET, LDO_ENABLE, PMIC_IRQ, PMIC_MODE0, and PMIC_MODE1 pins. This rail provides a wake source even when power to other rails is removed, allowing the MCU to wake up from one of the deep power-down modes.
4. V_{DD_IOn} supplies the GPIO pins of the MCU. V_{DDIO_0}, V_{DDIO_1}, V_{DDIO_2}, and V_{DDIO_4} provide 1.8 V, and V_{DDIO_3} provides a supply voltage of up to 3.6 V.

 

Investigating the Power Modes of the i.MX RT500 MCU

Modern MCUs typically provide a number of operating modes that exchange power consumption for performance. At the highest power settings, the maximum functionality is available with the CPU, memories, and on-chip peripherals all enabled and running at the highest possible clock frequency. To reduce power consumption, sleep and power-down modes are available to reduce clock frequencies, reduce supply voltages, and even completely power down unused sections of the MCU.

In the i.MX RT500 MCU, the built-in power management controller (PMC) allows fine-tuning the power input conditions to match the requirements of specific applications. For that purpose, the MCU allows using lower voltages on the VDDCORE rail when the chip runs at a lower clock frequency or when the device is in deep sleep mode. It’s possible to shut off the VDDCORE line completely when the chip is in a power-down mode. By default, the PMC sets the appropriate voltage level for the core logic. However, it’s possible to use an external PMIC combined with the PMIC pins of the MCU to achieve the same effect.

 

The power management module supports five power management modes (in order from highest to lowest power consumption):

1. Active
   The MCU powers up in active mode after reset, and embedded system engineers can change the default power configuration of the device by changing the values of specific system registers. The power configuration can be changed during runtime, for example, by using a dedicated power API. In this mode, the clocks to the CPU, memory, and peripherals are enabled, and most blocks may be in normal mode, a low-power mode, or off, as defined by the embedded application programmer. Furthermore, the active mode allows the system designers and programmers to fine-tune the power consumption by controlling which peripherals, memory blocks, and accessories remain active — section 8.4.1.1.1 of the i.MX RT500 reference manual provides further details on this.
    
2. Sleep
   In this mode, the PMC stops the clock to the system CPU, halting instructions until either a reset signal or an interrupt occurs. This mode allows developers to configure peripherals to continue their operation while the CPU remains suspended. These peripherals can generate interrupts that wake up the CPU and cause the MCU to return to the power mode defined by the PDRUNCFG and PSCCTL registers. While asleep, the CPU maintains the values of its internal registers and the SRAM. The logic levels of the I/O pins also remain static unless active peripherals change their state. Therefore, this power mode eliminates the dynamic power used by the CPU, memory system, and the internal bus. Note that sleep mode doesn’t change the CPU clock — it only disables the clock for the CPU.
    
3. Deep-Sleep
   This mode disables the clocks to the CPUs and, if not configured otherwise, also shuts down the clock signals of the on-chip peripherals and analog blocks. Embedded programmers are free to configure individual blocks to operate in their normal, low-power, or off state through software. Device registers and enabled SRAM sections retain their values. The power profiles API allows selected peripherals, such as USB, DMIC, SPI, I2C, USART, WWDT, RTC, and the micro-tick timer to remain active in deep sleep mode. Section 8.4.1.3.1 of the i.MX RT500 reference manual provides further details on deep-sleep mode.
    
4. Deep power-down
   In this mode, the power supply and all clocks are disabled for the entire chip except for the RTC. This measure means that the SRAM and registers, except those in the RTC module, can’t retain their values. Furthermore, all function pins are tri-stated as long as the device is powered externally. There are no further configuration options for this mode.
    
5. Full deep power-down
   This mode disables all external supplies except for VDD_AO18, VDD_AO1V8, and VDD_EAO. Wake-up sources may trigger a POR in the VDD1V8 and VDDCORE domains.

Waking up from states 4 and 5 goes through the entire RESET process. 

The MCU has dedicated PMIC_MODE pins to communicate state changes to an external PMIC when switching between states. Initially, there’s only one pre-defined state for these pins, and embedded programmers have to configure the PMIC_MODE pins through software. In active mode, the MCU takes control over the PMIC_MODE pins. When the MCU operates in one of the reduced power modes, the external PMIC takes control. Refer to section 8.4.2.1 of the reference manual for further details.

 

The Wake-Up Process and Typical Wake-Up Times

Intuitively, MCUs take longer to wake up from the deeper sleep modes than the sleep modes with more peripherals and circuitry enabled. The power supplies must stabilize and the crystal oscillators must startup to allow the re-enabled circuits to function properly. In deeper sleep modes, there are often limited sources available to wake up the MCU

For the i.MX RT500, the typical wake-up time from sleep mode with a system clock of 200 MHz is around 150 µs. From deep-sleep mode, the device takes about 120 µs to wake up. Waking the MCU up from full deep power-down state takes approximately 8.64 milliseconds due to the RESET sequence. Note that these timings are not guaranteed, and some restrictions apply. Refer to the official datasheet, section 1.3.4, for further details and the test conditions. It’s also important to note that the chip always wakes up to the active mode.

To wake the MCU up when it’s in a low-power mode, the embedded programmer has to configure one or more wake-up sources. In sleep mode, any peripheral that causes an interrupt and HWWAKE (Flexcomm Interfaces and DMIC subsystem activity) can wake up the MCU, as discussed earlier. In deep-sleep mode, various wake-up sources, such as pin interrupts, the reset pin, Flexcomm peripherals, DMA, DMIC, HWWAKE, SDIO, HASH-AES, CASPER, PowerQuad, ADC, DSP, USB, and ACMP can wake up the MCU. Besides these wake-up sources, various timers, such as the watchdog timer, the RTC, the uTick timer, and the OS Event timer can also cause the MCU to return from sleep mode periodically. When the MCU is in the deep power-down mode, the RTC and a system reset are the only ways to wake up the device.

 

Dynamic and Static Power Consumption of I/O Pins

The I/O pins are an often overlooked aspect of total power consumption. The I/O pins can contribute to the total static and dynamic power consumption. Depending on each pin’s internal pull-resistor setting and the voltage level, a static current may flow and increase the overall power consumption of the device. The I/O pins also contribute to the dynamic power requirements of the MCU whenever they are switching. Many times an MCU datasheet’s power numbers do not even include any I/O pin power consumption because it is application dependent on the external loads and switching frequency of the I/Os.

The different power modes of the i.MX RT500 MCU affect various on-chip peripherals and automatically disable some of the circuitry on the device to reduce its overall power consumption. Note that most GPIO pins have their internal pull-up and pull-down resistors and input buffer disabled on reset. For example, some pins have a different configuration to allow easier debugging. However, this behavior results in unused GPIO pins defaulting to their high-impedance mode with the respective input buffers disabled on reset unless otherwise specified by the programmers in the IOCON register. In deep power-down mode, the I/O pins are floating by default.

 

Power Consumption in Sleep Mode and Deep-Sleep Mode

Let’s now use the i.MX RT500 MCU to get some specifics on how a system’s main clock frequency and voltage on V_DDCORE affect the overall power consumption of the device:

 

 

The deep sleep and deep power-down modes disable the main CPU clock, and it’s also possible to shut down regions of the SRAM, which impacts the overall supply current requirements of the part. The following table lists the supply current for the active power rails in deep sleep mode with 128 KB of SRAM powered on, the internal LDO disabled, the array on, and periphery switched off at an ambient temperature of around 25 °C:

 

 

Therefore, the typical current consumption of the device is around 70 micro Amperes in deep sleep mode. Please refer to tables 11 and 12 in the device’s datasheet for further details and the exact test conditions. When the MCU is in the deep power-down or full deep power-down mode, the typical supply current is around 15 µA.

 

SRAM Power Saving Considerations

Power management must also consider the on-chip memories. For nonvolatile memories like Flash, the memories can be powered down without any loss of the contents. For SRAM, the embedded designer will have to decide if the contents of the memory need to be preserved when using a low power mode. Thankfully, many MCU products allow the designer to choose between maximum power savings with full data loss and reduced power savings with full data retention.

The i.MX RT500 device contains up to five megabytes of on-chip static RAM divided into up to 32 separate partitions. Each partition is accessible to both CPUs, both DMA engines, and all other AHB bus masters. Besides other features, it’s possible to independently place each block in a low-power retention mode or power it off completely to reduce the overall power consumption of the device. This action is possible because each memory partition consists of the memory block itself and the periphery required to interface the memory array itself. Embedded application designers can save power by turning the periphery off while retaining the contents of the memory array itself.

Taking this into consideration, embedded programmers should understand that lower SRAM partitions tend to save power relative to their higher counterparts, as each SRAM partition’s physical location within the device leads to current consumption variations:

 

Figure 2. Developers should favor using the lower SRAM partitions over the higher ones when trying to reduce the overall power consumption of the MCU. Image courtesy of NXP.

 

The i.MX RT500 Power Management application note and the i.MX RT500 family reference manual discuss various power-saving measures in more detail.

 

i.MX RT500 MCUs for Power Control and Power Management

Preserving power is crucial when designing any project. The i.MX RT500 crossover MCU offers power control and power management functionalities that allow the devices to operate while requiring as little power as possible efficiently. In active mode, the clocks to the CPU, memory, and peripherals are enabled, and most blocks may be in normal mode, a low-power mode, or off, as defined by the embedded application programmer. 

NXP’s website offers more information on the i.MX RT500 capabilities and applications. It also provides different training materials such as application notes, videos, and on-demand webinars.

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