Digital ICs News, Projects & Technical Articles

Ultra-Low Jitter: A Programmable Oscillator with Internal EEPROM from Texas Instruments

4 days ago in News by Mark Hughes

Implementing a Binary Parity Generator and Checker with GreenPAK

June 12, 2018 in Industry Articles by Dialog Semiconductor

Side-Wettable Flanks Enable AOI on Leadless SMD (DFN) Packages

May 31, 2018 in Industry Articles by Hans-Jürgen Funke, Nexperia

How to Design Schmitt Trigger Oscillators

May 24, 2018 in Technical Articles by Eduardo Corpeño

Pipelined Direct Form FIR Versus the Transposed Structure

May 21, 2018 in Technical Articles by Steve Arar

Considerations for FPGA Implementation of Linear-Phase FIR Filters

May 17, 2018 in Technical Articles by Steve Arar

Introduction to Distributed Arithmetic

May 11, 2018 in Technical Articles by Steve Arar

Basic Binary Division: The Algorithm and the VHDL Code

May 09, 2018 in Technical Articles by Steve Arar

Stanford Researchers Learn More about the Promise of Superconductors with Strontium Titanate

May 07, 2018 in News by Donald Krambeck

Use the Xilinx CORDIC Core to Easily Generate Sine and Cosine Functions

May 02, 2018 in Technical Articles by Steve Arar

How Does Xilinx Use Its Logic Fabric to Implement Efficient Multipliers?

April 30, 2018 in Technical Articles by Steve Arar

T Is for Toggle: Understanding the T Flip-Flop

April 17, 2018 in Technical Articles by Robert Keim

How to Use Carry-Save Adders to Efficiently Implement Multioperand Addition

April 13, 2018 in Technical Articles by Steve Arar

How to Use VHDL Components to Create a Neat Hierarchical Design

April 06, 2018 in Technical Articles by Steve Arar

Controlling Permanent Magnet Synchronous Motors: A Highly-Integrated IC from Infineon

April 05, 2018 in News by Nick Davis

How to Write the VHDL Description of a Simple Algorithm: The Control Path

March 16, 2018 in Technical Articles by Steve Arar

How to Write the VHDL Description of a Simple Algorithm: The Data Path

March 15, 2018 in Technical Articles by Steve Arar

How to Reduce Power Consumption with Clock Gating

March 08, 2018 in Technical Articles by Steve Arar

Encoding the States of a Finite State Machine in VHDL

March 05, 2018 in Technical Articles by Steve Arar

Incomplete If Statements and Latch Inference in VHDL

February 23, 2018 in Technical Articles by Steve Arar