The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs
The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs
Announced today, the new ChipStack AI Super Agent from Cadence automates front end silicon design and verification,…
Announced today, the new ChipStack AI Super Agent from Cadence automates front end silicon design and verification, delivering a 10X productivity increase.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
Enjoy this selection of fascinating technology news from the recent Electronica 2024 trade show in Munich, Germany.
Enjoy this selection of fascinating technology news from the recent Electronica 2024 trade show in Munich, Germany.
Learn how to implement finite-state machines in VHDL by creating a 4-bit binary counter. After compiling, it will run on…
Learn how to implement finite-state machines in VHDL by creating a 4-bit binary counter. After compiling, it will run on an Altera CPLD development board connected to a custom PCB with input switches and an LED display.
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
The Keysight EDA 2024 tool suite promises to provide end-to-end design, modeling. and simulation with “shift left”…
The Keysight EDA 2024 tool suite promises to provide end-to-end design, modeling. and simulation with “shift left” workflow tools designed to increase productivity in the RF/5G world.
Angstrom-scale ICs will require innovation across the entire semiconductor ecosystem: This will include advances in both…
Angstrom-scale ICs will require innovation across the entire semiconductor ecosystem: This will include advances in both the hardware (transistors, power distribution, and connection of multi-die systems) and tools (EDA tools with AI/ML and silicon life-cycle management).
A slew of new electronic design automation (EDA) tools and resources for IC design and verification were debuted at last…
A slew of new electronic design automation (EDA) tools and resources for IC design and verification were debuted at last week’s DAC 2023 event. Here’s a sampling.
The company positions the new chiplet-based SoC as well suited for todays’ ever more complex chip designs.
The company positions the new chiplet-based SoC as well suited for todays’ ever more complex chip designs.
What happens when you mix a venture capitalist with a background in hardware development at Apple with two engineers with…
What happens when you mix a venture capitalist with a background in hardware development at Apple with two engineers with Harvard MBAs? Allspice: a Git-style collaboration environment that brings software best practices to hardware design.
Stelios Diamantidis, a Distinguished Architect at Synopsys, is leading efforts to apply artificial intelligence to…
Stelios Diamantidis, a Distinguished Architect at Synopsys, is leading efforts to apply artificial intelligence to integrated circuit design and optimization of the next generation of CPUs, GPUs, and memories.
At today’s Synopsys Users Group (SNUG) event, Synopsys has unveiled a full-stack suite of AI-based EDA tools.
At today’s Synopsys Users Group (SNUG) event, Synopsys has unveiled a full-stack suite of AI-based EDA tools.
With products built on some of the most advanced semiconductor fab processes—like TSMC’s 7 nm node—fabless…
With products built on some of the most advanced semiconductor fab processes—like TSMC’s 7 nm node—fabless FPGA/eFPGA providers are rolling out new updated open-source tools, new devices, and new IP.
Seeking to leverage today’s data-rich engineering world, Siemens has released Questa Verification IQ, a software…
Seeking to leverage today’s data-rich engineering world, Siemens has released Questa Verification IQ, a software platform enabling data-driven IC verification.
How do you begin by building world-record robots and end up trying to revolutionize the electronics industry? Dr. Duncan…
How do you begin by building world-record robots and end up trying to revolutionize the electronics industry? Dr. Duncan Haldane, co-founder and CEO of JITX, retraces his fascinating career path and describes their vision for a better circuit design process.
Keen to free industrial robotics from the burdens of custom design, AMD has launched a SOM-based starter kit that puts…
Keen to free industrial robotics from the burdens of custom design, AMD has launched a SOM-based starter kit that puts ROS 2 and predefined interface apps into play.
This article covers undesired switching events, known as hazards, that can occur when developing combinational logic circuits.
This article covers undesired switching events, known as hazards, that can occur when developing combinational logic circuits.
Gate-level implementation of logic functions is limited by the gate fan-in. This article examines logic factoring,…
Gate-level implementation of logic functions is limited by the gate fan-in. This article examines logic factoring, grouping, and level increases to implement logic functions with limited input gates.
The race for space has created a flood of innovations in space-rated tech. Hoping to strike gold with updatable FPGAs,…
The race for space has created a flood of innovations in space-rated tech. Hoping to strike gold with updatable FPGAs, Xilinx and STMicroelectronics have teamed up for a rad-hard solution.
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