The X7 runs on 2-5 W, connects over PCIe Gen 3 or USB 3.2, and uses the same CVflow engine already in over 50 million of the company’s AI SoCs.
The X7 runs on 2-5 W, connects over PCIe Gen 3 or USB 3.2, and uses the same CVflow engine already in over 50 million of the company’s AI SoCs.
The OAX7700 ASIC adds an NPU and pre-roll video capture to cut parking surveillance power consumption by 97%.
The OAX7700 ASIC adds an NPU and pre-roll video capture to cut parking surveillance power consumption by 97%.
Designing compact AI sensor nodes forces signal integrity and thermal management to compete for limited PCB copper,…
Designing compact AI sensor nodes forces signal integrity and thermal management to compete for limited PCB copper, creating severe PDN and thermal bottlenecks.
After building a $10B+ smartphone business, Yenchi Lee is standing up MediaTek's Datacenter BU from scratch to tackle…
After building a $10B+ smartphone business, Yenchi Lee is standing up MediaTek's Datacenter BU from scratch to tackle full-stack AI silicon, 2.5D packaging, and co-packaged optics.
The RZ/G3L and RZ/G3SE share a pin-compatible package platform and 1-mW-level standby power.
The RZ/G3L and RZ/G3SE share a pin-compatible package platform and 1-mW-level standby power.
A new addition to Nvidia's CUDA-Q quantum computing platform adds logical qubit error correction and abstraction to…
A new addition to Nvidia's CUDA-Q quantum computing platform adds logical qubit error correction and abstraction to significantly speed reliable quantum application development.
Recent semiconductor business moves from Nvidia, MediaTek, GlobalFoundries, Qualcomm, Amazon, and Analog Devices…
Recent semiconductor business moves from Nvidia, MediaTek, GlobalFoundries, Qualcomm, Amazon, and Analog Devices highlight growing investment in AI infrastructure, quantum manufacturing, optical connectivity, and edge intelligence.
John Koeter, former SVP of IP at Synopsys (retired), joins the podcast to discuss how pre-designed silicon blocks are…
John Koeter, former SVP of IP at Synopsys (retired), joins the podcast to discuss how pre-designed silicon blocks are accelerating chip development in the age of AI and 3D ICs.
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring…
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring flagship AI performance to fanless Googlebooks.
Nexperia NSF0x0120 N-Channel SiC MOSFETs deliver high-voltage switching performance for demanding power conversion…
Nexperia NSF0x0120 N-Channel SiC MOSFETs deliver high-voltage switching performance for demanding power conversion applications. Watch and learn all about their features, specs, applications, and more!
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end…
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end compute and proactive mobile intelligence.
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development…
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development platform, and a system-level reference architecture to eliminate tail latency, maximize power efficiency, and scale agentic AI clusters.
M6 is Apple's first 2-nm chip and features a dual 16-core Neural Engine, while the M5 Ultra joins four dies to achieve…
M6 is Apple's first 2-nm chip and features a dual 16-core Neural Engine, while the M5 Ultra joins four dies to achieve 1.2 TB/s of unified memory bandwidth.
The Q-2390 and IQ-2390 share a Cortex-A78/A55 complex, an Adreno 704 GPU, and an optional RISC-V real-time core, with the…
The Q-2390 and IQ-2390 share a Cortex-A78/A55 complex, an Adreno 704 GPU, and an optional RISC-V real-time core, with the industrial part introducing the IQ2 Series.
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4…
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4 platform provide specialized architectures for agentic AI workloads across various domains.
The 2-nm processor runs Arm and z/Architecture instructions natively on the same core.
The 2-nm processor runs Arm and z/Architecture instructions natively on the same core.
RackCommander groups MaxLinear's USB UARTs, RS-485 transceivers, GPIO expanders, and power devices for rack-level management.
RackCommander groups MaxLinear's USB UARTs, RS-485 transceivers, GPIO expanders, and power devices for rack-level management.
Companies across industries are leveraging tech from NXP, MaxLinear and Nordic Semiconductor on automotive UWB,…
Companies across industries are leveraging tech from NXP, MaxLinear and Nordic Semiconductor on automotive UWB, accelerated OpenZFS storage, and low-power Bluetooth Mesh sensing.
In this edition of Business Shorts, we spotlight five announcements that show AI demand is reshaping everything from Wall…
In this edition of Business Shorts, we spotlight five announcements that show AI demand is reshaping everything from Wall Street financing to washing machines.
The new MCX A5 MCUs integrate 10BASE-T1S Ethernet, topology discovery, and post-quantum security to streamline and…
The new MCX A5 MCUs integrate 10BASE-T1S Ethernet, topology discovery, and post-quantum security to streamline and protect industrial edge networks.
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