Learn how EPC’s multi-stage ISOP architecture uses low-voltage GaN FETs to efficiently convert 800 V DC in AI data centers, reducing output ripple and…
Learn how EPC’s multi-stage ISOP architecture uses low-voltage GaN FETs to efficiently convert 800 V DC in AI data centers, reducing output ripple and capacitance while achieving up to 98.5% efficiency.
Recent semiconductor business moves from Nvidia, MediaTek, GlobalFoundries, Qualcomm, Amazon, and Analog Devices…
Recent semiconductor business moves from Nvidia, MediaTek, GlobalFoundries, Qualcomm, Amazon, and Analog Devices highlight growing investment in AI infrastructure, quantum manufacturing, optical connectivity, and edge intelligence.
Announced today by AtlasBase, Thalia is a 5.6B-well bio-silicon chip that uses synthetic DNA to break power and density…
Announced today by AtlasBase, Thalia is a 5.6B-well bio-silicon chip that uses synthetic DNA to break power and density bottlenecks in AI data center storage and molecular computing.
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring…
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring flagship AI performance to fanless Googlebooks.
New T&M tools from Rohde & Schwarz, Tektronix, and Teradyne target packaged-goods inspection, HDMI and automotive…
New T&M tools from Rohde & Schwarz, Tektronix, and Teradyne target packaged-goods inspection, HDMI and automotive compliance testing, and advanced AI semiconductor testing.
By embedding heterogeneous Si, SiC, and GaN die directly into 12-inch silicon wafers with precision RDLs, Onsemi's EPP…
By embedding heterogeneous Si, SiC, and GaN die directly into 12-inch silicon wafers with precision RDLs, Onsemi's EPP replaces wire bonds and mold compounds to deliver up to 5x power density.
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end…
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end compute and proactive mobile intelligence.
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development…
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development platform, and a system-level reference architecture to eliminate tail latency, maximize power efficiency, and scale agentic AI clusters.
M6 is Apple's first 2-nm chip and features a dual 16-core Neural Engine, while the M5 Ultra joins four dies to achieve…
M6 is Apple's first 2-nm chip and features a dual 16-core Neural Engine, while the M5 Ultra joins four dies to achieve 1.2 TB/s of unified memory bandwidth.
Cut complex, power-hungry DDR. A Zephyr-first design on PolarFire SoC FPGAs leverages on-chip scratchpad and low-power…
Cut complex, power-hungry DDR. A Zephyr-first design on PolarFire SoC FPGAs leverages on-chip scratchpad and low-power alternatives to boost efficiency and lower BoM costs.
The new evaluation kits aim to lower the barrier for on-device AI development with Alif’s AI/ML hardware-accelerated…
The new evaluation kits aim to lower the barrier for on-device AI development with Alif’s AI/ML hardware-accelerated Ensemble and Balletto MCUs.
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4…
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4 platform provide specialized architectures for agentic AI workloads across various domains.
Learn how MEMS sensor technology brings edge AI and vibration monitoring to smart manufacturing, enabling early defect…
Learn how MEMS sensor technology brings edge AI and vibration monitoring to smart manufacturing, enabling early defect detection and predictive maintenance to prevent downtime.
Select Versal RF Series devices will be AMD's first adaptive SoCs with native UCIe 1.1 interfaces, allowing designers to…
Select Versal RF Series devices will be AMD's first adaptive SoCs with native UCIe 1.1 interfaces, allowing designers to co-package third-party chiplets.
RackCommander groups MaxLinear's USB UARTs, RS-485 transceivers, GPIO expanders, and power devices for rack-level management.
RackCommander groups MaxLinear's USB UARTs, RS-485 transceivers, GPIO expanders, and power devices for rack-level management.
Companies across industries are leveraging tech from NXP, MaxLinear and Nordic Semiconductor on automotive UWB,…
Companies across industries are leveraging tech from NXP, MaxLinear and Nordic Semiconductor on automotive UWB, accelerated OpenZFS storage, and low-power Bluetooth Mesh sensing.
In this edition of Business Shorts, we spotlight five announcements that show AI demand is reshaping everything from Wall…
In this edition of Business Shorts, we spotlight five announcements that show AI demand is reshaping everything from Wall Street financing to washing machines.
The new PolarFire FPGA-powered board from Microchip brings multiple sensors to Nvidia edge AI platforms.
The new PolarFire FPGA-powered board from Microchip brings multiple sensors to Nvidia edge AI platforms.
The rebuilt platform puts the previously closed cloud backend under an Apache 2.0 license and runs on AWS serverless…
The rebuilt platform puts the previously closed cloud backend under an Apache 2.0 license and runs on AWS serverless services in a customer's own account.
The controller, PHY, security, and verification IP support 128 GT/s links and target rack-scale memory pools exceeding 100 TB.
The controller, PHY, security, and verification IP support 128 GT/s links and target rack-scale memory pools exceeding 100 TB.
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