Launched today, Synopsys’ ESUN IP solution slashes AI tail latency and eliminates networking bottlenecks to enable seamless, scalable performance for modern AI…
Launched today, Synopsys’ ESUN IP solution slashes AI tail latency and eliminates networking bottlenecks to enable seamless, scalable performance for modern AI infrastructure.
The new system-on-chip pairs a heterogeneous AI compute engine with a low-latency multi-camera image signal processor,…
The new system-on-chip pairs a heterogeneous AI compute engine with a low-latency multi-camera image signal processor, and can ship pre-integrated with emotion3D perception software.
The Korean unicorn packages four NPU dies with 144 GB of HBM3E and bets on an open software stack to serve large language…
The Korean unicorn packages four NPU dies with 144 GB of HBM3E and bets on an open software stack to serve large language models at lower cost per token.
The next-generation XR chipset delivers up to 48 TOPS of on-device AI and 4.4K-per-eye visuals. The device will debut…
The next-generation XR chipset delivers up to 48 TOPS of on-device AI and 4.4K-per-eye visuals. The device will debut this fall in XREAL's Project Aura glasses.
Announced today, the all-in-one VL53L9CX combines stacked BSI SPAD technology, metasurface optics, and on-chip processing…
Announced today, the all-in-one VL53L9CX combines stacked BSI SPAD technology, metasurface optics, and on-chip processing to deliver dense spatial awareness directly to small microcontrollers.
Lotus Microsystems, Oriole Networks, and Atomera have each rolled out technologies tackling the physical limits slowing…
Lotus Microsystems, Oriole Networks, and Atomera have each rolled out technologies tackling the physical limits slowing AI infrastructure.
The new XpressConnect PCIe 6.0 and CXL 3.1 Retimers reign in signal integrity challenges in AI data centers and other…
The new XpressConnect PCIe 6.0 and CXL 3.1 Retimers reign in signal integrity challenges in AI data centers and other high-bandwidth installations.
The new Elite Pairing Studio is an interactive cloud-based simulation tool designed to give power electronics engineers…
The new Elite Pairing Studio is an interactive cloud-based simulation tool designed to give power electronics engineers deep visibility into device-level switching behavior and component trade-offs.
France’s Électronique 2030 program commits €5B+ to revitalize its semiconductor industry. Learn the details of this…
France’s Électronique 2030 program commits €5B+ to revitalize its semiconductor industry. Learn the details of this ambitious effort, and the market challenges it’s facing.
At Computex, Intel described the CPU as the control plane for agentic workloads, pairing new processors and network…
At Computex, Intel described the CPU as the control plane for agentic workloads, pairing new processors and network controllers with fresh details on its inference GPU.
The 88-core Vera processor introduces Spatial Multithreading and a claimed 1.8x task-completion lead over x86 processors.
The 88-core Vera processor introduces Spatial Multithreading and a claimed 1.8x task-completion lead over x86 processors.
AI-driven data demands are outpacing traditional HDDs. System developers must migrate to high-performance, secure, and…
AI-driven data demands are outpacing traditional HDDs. System developers must migrate to high-performance, secure, and efficient NVMe SSDs to scale for AI workloads.
New characterization software delivers 7x throughput gains by combining a predictive AI engine with a purpose-built SPICE…
New characterization software delivers 7x throughput gains by combining a predictive AI engine with a purpose-built SPICE simulator.
At Computex 2026, the company is expanding its Edge AI ecosystem by introducing the Snapdragon C Platform for entry-level…
At Computex 2026, the company is expanding its Edge AI ecosystem by introducing the Snapdragon C Platform for entry-level laptops, and the Dragonwing IQ10 Reference Design for robotics.
The bottleneck limiting the next generation of artificial intelligence isn't compute power—it's the wire connecting the…
The bottleneck limiting the next generation of artificial intelligence isn't compute power—it's the wire connecting the chips. French startup Scintil Photonics thinks it has the answer.
Learn how eUSB2V2-based enabling technology for next-generation AI PC web cameras delivers the high bandwidth, local…
Learn how eUSB2V2-based enabling technology for next-generation AI PC web cameras delivers the high bandwidth, local intelligence, and power efficiency required for emerging edge AI use cases.
Broadcom’s high-integration Wi-Fi 8 & NPU-accelerated 50G PON gateway SoCs aim to build a cohesive, 50 Gbps broadband…
Broadcom’s high-integration Wi-Fi 8 & NPU-accelerated 50G PON gateway SoCs aim to build a cohesive, 50 Gbps broadband access ecosystem for the AI-infused home.
Edge AI moves is moving processing to harsh environments like UAVs and robotics. Connectors must be rugged, compact, and…
Edge AI moves is moving processing to harsh environments like UAVs and robotics. Connectors must be rugged, compact, and high-power to meet SWaP-C constraints and ensure safety/reliability.
A South Korean startup, KoolMicro, is betting that liquid cooling built into the chip package itself is the only way to…
A South Korean startup, KoolMicro, is betting that liquid cooling built into the chip package itself is the only way to handle the next generation of GPU heat loads.
Edge AI success is limited by memory and power. Fragmented tools cause failures. Learn how a cohesive, full-lifecycle…
Edge AI success is limited by memory and power. Fragmented tools cause failures. Learn how a cohesive, full-lifecycle approach unifying design and deployment is essential for scalable systems.
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