Latest FPGA Articles and Videos

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Cadence Releases First ECAD Platform Dedicated to 3D System Design

The Cadence Integrity 3D-IC platform brings together a suite of advanced floor planning and validation software to develop 3D-stacked SoC designs.

October 12, 2021 by Adrian Gibbons

Why Physical Verification Is Only Getting Tougher With Advanced Nodes

In the nanometer era, IC complexity grows faster than die areas. EDA companies are stepping up with tools to streamline physical verification.

April 14, 2021 by Antonio Anzaldua Jr.

What Is Mixed-Signal IC Design?

This brief gives an overview of the steps in a typical mixed-signal IC design flow.

December 07, 2020 by Jean-Jacques DeLisle

What Is Digital IC Design?

Learn the high-level overview of digital integrated circuit (IC) design.

December 02, 2020 by Jean-Jacques DeLisle

Boosting Memory Performance in the Age of DDR5: An Intro to DDR Training Modes

Analysts predict that DDR5 will dominate the DRAM market in coming years. How do you calibrate DDR for peak memory performance?

November 06, 2020 by Dr. Steve Arar

Intel and Analog Devices Link Up to Streamline 5G Network Design

The two RF powerhouses have teamed up to create a flexible radio platform that addresses 5G network design challenges.

August 05, 2020 by Jake Hertz

Ep.3 | Innovating Aerospace: SpaceX’s Culture of Rapid Prototyping

SpaceX has achieved incredible, historic strides in aerospace. For the engineers and designers who work there, part of the formula for success is rapid prototyping.

June 11, 2020 by Dave Finch

Google Proposes AI as Solution for Speedier AI Chip Design

One of the trickiest aspects of chip design is figuring out how to pack more circuitry into a smaller footprint while maintaining power, speed, and energy efficiency.

April 06, 2020 by Luke James

Osaka University Develops an FPGA Computing Device for Maximal Optimization of AI Tasks

Osaka University researchers have built a new device that can be customized by the user for maximum efficiency in AI applications.

March 13, 2020 by Luke James

The Importance of Reliability Verification in AI/ML Processors

With the adoption of artificial intelligence and machine learning in a wide variety of applications, reliability verification of AI/ML processors is critical since failures can have major consequences for the validity and legitimacy of AI/ML technology.

January 21, 2020 by Neel Natekar, Mentor

Microchip High-Speed Synchronous Buck Controllers | New Product Brief

This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.

November 28, 2019 by Mouser Electronics

How RISC-V Security Stacks Strengthen Computer Architecture

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.

November 26, 2019 by Ted Speers, Microchip

Synopsys and NSITEXE Partnership Finds Success with Accelerated Processor SoC Development

NSITEXE utilizes Synopsys’ development tools and IP to build a SoC (system-on-a-chip) for autonomous driving.

September 09, 2019 by Gary Elinoff

IC Design Resources Roundup: Mentor, Cadence, and Synopsys

The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.

August 05, 2019 by Gary Elinoff

Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

July 09, 2019 by Ted Marena, Western Digital

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

March 20, 2019 by Ted Marena, Western Digital

How to Utilize the RISC-V Instruction Set CKB-VM

Part 3 of this series shows examples of the CKB-VM, a RISC-V instruction set based VM, in action in three different ways.

March 19, 2019 by Xuejie Xiao, Nervos

CKB-VM as a RISC-V Instruction Set: Inspiration, Design, and Benefits

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

March 12, 2019 by Xuejie Xiao, Nervos

Introduction to the RISC-V Instruction Set CKB-VM and its Requirements

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.

March 05, 2019 by Xuejie Xiao, Nervos

Clock Signals in FPGA Design: Data Path Maximal Clock Rates and the Xilinx PERIOD Timing Constraint

This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock signal that will be used with an FPGA design.

December 05, 2018 by Dr. Steve Arar