At Its Innovators Day Event, Altera Unveils Expanded Agilex FPGA Portfolio

Today, at its annual Altera Innovators Day developer conference, Altera unveiled a slew of announcements across its hardware and software offerings. Most notably, the company shared that all Agilex FPGA and SoC FPGA families have reached production availability.

This includes the high-end Agilex 9, the broadly targeted Agilex 7, the mid-range Agilex 5, and the cost-optimized Agilex 3. All About Circuits spoke with Venkat Yadavalli, VP and GM of Altera’s Business Management Group, to learn more about the news firsthand.

Architectural Advances in the Agilex 5 D-Series

The most significant hardware update came with the introduction of higher-density Agilex 5 D-Series devices. Specifically, Altera has increased logic density by up to 2.5 times compared to prior devices in the same family, making the largest D-Series device now support 1.6 million logic elements, coupled with a higher ratio of DSP blocks infused with AI tensor compute capabilities.

The architecture distributes these capabilities throughout the programmable fabric, rather than concentrating them in hardened blocks to give developers more granular control when mapping workloads.

Updates to the Agilex 5 D-Series

As Yadavalli explains, “Previously, when we announced the Agilex 5, we had the D-Series product, which was going all the way up to about 640 KLEs. Now we worked hard to increase the logic, memory, as well as AI compute capabilities by 2.5x.”

This increase is intended to address applications where both compute throughput and bandwidth are gating factors, such as real-time 4K and 8K video pipelines and edge inference engines that cannot tolerate high latency.To support these data-intensive tasks, the D-Series also doubles memory throughput, with DDR5 interfaces now operating at up to 5,600 MT/s, while LPDDR5 interfaces reach 5,500 MT/s per instance.

Quartus Prime Software 25.3

The hardware updates coincide with the release of Quartus Prime Pro Edition version 25.3, which Altera positioned as reducing the complexity of FPGA adoption. A highlight of this release is the introduction of Visual Designer Studio, which is Altera’s fourth-generation system integration environment designed to accelerate IP block connectivity and design entry.

The tool features a drag-and-drop block-level interface that automatically validates interconnects between IP components and RTL code. It also traces data paths across the device to help designers debug architectures visually.

Altera claims that Visual Designer Studio reduces design start-up time from approximately five days to two hours compared to RTL-only flows. According to them, the automation of IP routing and the real-time validation of interconnects are intended to minimize the likelihood of functional errors at the integration stage, effectively shortening timing closure cycles later in development.

Altera’s Visual Designer Studio is said to reduce start-up time from days to hours.

Beyond the new design studio, Quartus 25.3 extends Altera’s compiler optimizations. Average compile times have improved by 6% compared to version 25.1.1, resulting in an overall 27% reduction since Agilex 7 entered production. Designs also consume approximately 6% fewer Adaptive Logic Modules while maintaining Fmax targets.

Yadavalli remarks, “With 25.3, compiles will be 27% faster and also use fewer resources while getting a better Fmax.”

“What it means is that engineers can continue to pack in more into an existing device, and we can really give the utilization at a very high level, which is unprecedented.”

Security and Post-Quantum Cryptography

In parallel with the logic and memory enhancements, Altera has embedded post-quantum cryptography (PQC) secure boot capability into all Agilex 5 D-Series devices. The addition builds on existing design security features such as bitstream encryption, device authentication, and anti-tamper measures, but shifts the security baseline toward resilience against quantum-enabled attacks.

As Yadavalli describes, “We also started to recognize that there is evolution in the security standards, and we started to bring in the post-quantum crypto capabilities as well, in addition to already many different security aspects that we have bolstered Agilex with.”

According to Altera, the PQC integration functions as a hardware root of trust. During power-up, the device verifies the authenticity of the boot image using quantum-resistant digital signatures before executing any code.

This ensures that only verified firmware and bitstreams can configure the device, preventing adversaries from injecting malicious images, even if quantum computing renders today’s cryptography obsolete.

Implications for the FPGA Market?

FPGA vendors across the industry are responding to the twin pressures of AI-driven workloads and escalating ASIC development costs. Rising mask and verification costs have increased demand for programmable devices that offer performance and flexibility, especially in applications where standards evolve quickly.

To this point, Yadavalli puts FPGAs into perspective.

“FPGAs are always the innovation platform wherever there are evolving standards and workloads as things start changing, and that makes them the platform of choice for the next generation of edge and AI solutions.”

With its expanded Agilex portfolio and upgraded toolchain, Altera hopes its FPGAs can answer this call as the industry continues to mature.

All images used courtesy of Altera.