Many evolutionary changes have allowed DRAM cell size to shrink to 0.0020 um2. At sub-15nm nodes, DRAM designs require optimization to avoid some of the common failure modes like Variable Retention Time, Sensing Fails, Row Hammer, Row Press, and Sensing Fails.
In partnership with Neumonda
The standard DRAM tests of memory manufacturers often don’t meet industrial requirements. The new Rhinoe tester from NEUMONDA conducts vendor-independent tests that simulate the environment the DRAM will be used in to predict potential failures. All this at a fraction of the costs of traditional testers. This is unique.
In partnership with Neumonda
Dr. Peter Wawer brings insights from a distinguished career that has touched three unique major semiconductor technologies: silicon photovoltaics, embedded Flash, and now wide bandgap semiconductors for power electronics.
May 16, 2023 by Daniel Bogdanoff