Announced today, Altera has a new FPGA portfolio along with an AI expert companion designed to accelerate development for next-generation digital and physical AI fabrics.
Announced today, Altera has a new FPGA portfolio along with an AI expert companion designed to accelerate development for next-generation digital and physical AI fabrics.
Asian Development Bank (ADB) is advancing Asia's semiconductor sector by expanding workforce training in Thailand and…
Asian Development Bank (ADB) is advancing Asia's semiconductor sector by expanding workforce training in Thailand and offering financial de-risking tools to strengthen supply chain resilience.
Efinix expands its Sapphire RISC-V SoC family with a configurable 64-bit processor offering larger memory support, Linux…
Efinix expands its Sapphire RISC-V SoC family with a configurable 64-bit processor offering larger memory support, Linux capability and FPGA acceleration for embedded and edge AI designs.
In this interview article, Renesas VP Peter Jenkins discusses how the company is leveraging its automotive sensor…
In this interview article, Renesas VP Peter Jenkins discusses how the company is leveraging its automotive sensor heritage and mixed-signal ICs to power the future of edge AI and humanoid robotics.
The SY757xx family translates clock inputs from 1.2 to 3.3 V down to 1.2 V LVCMOS outputs at frequencies up to 250 MHz,
The SY757xx family translates clock inputs from 1.2 to 3.3 V down to 1.2 V LVCMOS outputs at frequencies up to 250 MHz,
Learn how rising security threats, quantum computing, and strict regulations demand FPGA architectures with integral…
Learn how rising security threats, quantum computing, and strict regulations demand FPGA architectures with integral hardware security and crypto agility for long-term compliance.
The new PolarFire FPGA-powered board from Microchip brings multiple sensors to Nvidia edge AI platforms.
The new PolarFire FPGA-powered board from Microchip brings multiple sensors to Nvidia edge AI platforms.
The Titanium Edge FPGA family targets constrained edge AI with 50% lower power, compact SiP packages, high-speed MIPI…
The Titanium Edge FPGA family targets constrained edge AI with 50% lower power, compact SiP packages, high-speed MIPI I/O, and robust security/reliability features for intelligent systems.
The OECD is analyzing the semiconductor industry, focusing on supply chain resilience, global value chain mapping, and…
The OECD is analyzing the semiconductor industry, focusing on supply chain resilience, global value chain mapping, and the impact of rising industrial subsidies on global market competition.
Announced today, the new AMD Versal Premium Gen 2 MoP SoCs boost performance by integrating memory on-package. It cuts…
Announced today, the new AMD Versal Premium Gen 2 MoP SoCs boost performance by integrating memory on-package. It cuts board space by 60% while gaining 288 GB/s bandwidth and 15-year lifecycle.
France’s Électronique 2030 program commits €5B+ to revitalize its semiconductor industry. Learn the details of this…
France’s Électronique 2030 program commits €5B+ to revitalize its semiconductor industry. Learn the details of this ambitious effort, and the market challenges it’s facing.
An RTL glitch in an eFuse controller can permanently brick costly silicon. This article covers defense-in-depth FSM…
An RTL glitch in an eFuse controller can permanently brick costly silicon. This article covers defense-in-depth FSM design, redundant watchdogs, and formal SVA verification.
The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs
The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs
An audit finds that the European Chips Act is "very unlikely" to hit the 20% global market target by 2030, citing…
An audit finds that the European Chips Act is "very unlikely" to hit the 20% global market target by 2030, citing fragmented funding, slow progress on FOAKs, and fierce international competition.
HDLs are formal descriptions of behavior, making them software by definition. Modernizing these outdated tools is key to…
HDLs are formal descriptions of behavior, making them software by definition. Modernizing these outdated tools is key to making FPGA development more accessible and productive for all engineers.
Learn how the EU's premier lending institution is deploying billions in loans, equity, and blended finance to build a…
Learn how the EU's premier lending institution is deploying billions in loans, equity, and blended finance to build a sovereign European chip ecosystem.
To complete this project, we add backlight control and temperature-sensing functionality to the clock we built in the…
To complete this project, we add backlight control and temperature-sensing functionality to the clock we built in the previous installments.
We continue our design of a clock that uses analog ammeters to display time and temperature. In this installment, we…
We continue our design of a clock that uses analog ammeters to display time and temperature. In this installment, we examine the second of the two circuits that enable the timekeeping function.
This project turns old-school analog ammeters into a working clock that can also display the ambient temperature.
This project turns old-school analog ammeters into a working clock that can also display the ambient temperature.
In this exclusive interview, the Seattle startup says its software-ML-hardware co-design—announced today—converts…
In this exclusive interview, the Seattle startup says its software-ML-hardware co-design—announced today—converts off-the-shelf FPGA servers into high-efficiency AI inference engines.
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