Designing compact AI sensor nodes forces signal integrity and thermal management to compete for limited PCB copper, creating severe PDN and thermal bottlenecks.
Designing compact AI sensor nodes forces signal integrity and thermal management to compete for limited PCB copper, creating severe PDN and thermal bottlenecks.
This article describes a non-contact liquid level sensor using fringing field capacitance with the AnalogPAK IC, using…
This article describes a non-contact liquid level sensor using fringing field capacitance with the AnalogPAK IC, using Math Core calibration for improved stability.
Learn how EPC’s multi-stage ISOP architecture uses low-voltage GaN FETs to efficiently convert 800 V DC in AI data…
Learn how EPC’s multi-stage ISOP architecture uses low-voltage GaN FETs to efficiently convert 800 V DC in AI data centers, reducing output ripple and capacitance while achieving up to 98.5% efficiency.
As chipmakers stack dies vertically to meet surging AI demand, 2D imaging is losing its edge. Automated 3D reconstruction…
As chipmakers stack dies vertically to meet surging AI demand, 2D imaging is losing its edge. Automated 3D reconstruction is becoming essential to keeping fabs on pace.
Learn how rising security threats, quantum computing, and strict regulations demand FPGA architectures with integral…
Learn how rising security threats, quantum computing, and strict regulations demand FPGA architectures with integral hardware security and crypto agility for long-term compliance.
Legacy air-gapped ECAD systems struggle to support modern engineering teams. Learn how Zero Trust and GovCloud enclaves…
Legacy air-gapped ECAD systems struggle to support modern engineering teams. Learn how Zero Trust and GovCloud enclaves enable compliant collaboration on export-restricted hardware IP.
Cut complex, power-hungry DDR. A Zephyr-first design on PolarFire SoC FPGAs leverages on-chip scratchpad and low-power…
Cut complex, power-hungry DDR. A Zephyr-first design on PolarFire SoC FPGAs leverages on-chip scratchpad and low-power alternatives to boost efficiency and lower BoM costs.
Scaling down RF circuit footprints requires balancing board space against critical trade-offs. Discover how loading…
Scaling down RF circuit footprints requires balancing board space against critical trade-offs. Discover how loading methods and high-dielectric substrates impact Q factor and insertion loss.
Learn how MEMS sensor technology brings edge AI and vibration monitoring to smart manufacturing, enabling early defect…
Learn how MEMS sensor technology brings edge AI and vibration monitoring to smart manufacturing, enabling early defect detection and predictive maintenance to prevent downtime.
Explore common design-to-manufacturing gaps observed during pre-production engineering checks of FR-4 boards, from…
Explore common design-to-manufacturing gaps observed during pre-production engineering checks of FR-4 boards, from stackup imbalances to tight clearances.
Learn to decouple application logic from physical routing using a Board Support Package (BSP). This layered architecture…
Learn to decouple application logic from physical routing using a Board Support Package (BSP). This layered architecture accelerates prototyping and minimizes costly respins on custom boards.
Accelerator-based computing brings faster load changes, higher current density, and tighter thermal constraints,…
Accelerator-based computing brings faster load changes, higher current density, and tighter thermal constraints, requiring updates to rectifiers, DC/DC conversion, and battery backup.
As software-defined embedded systems evolve, dynamic storage architectures replace static partitioning to optimize flash…
As software-defined embedded systems evolve, dynamic storage architectures replace static partitioning to optimize flash efficiency, support long-term updates, and control rising hardware costs.
Skyrocketing SoC costs mean traditional testing can't catch every sub-7nm escape. Early formal verification, unified…
Skyrocketing SoC costs mean traditional testing can't catch every sub-7nm escape. Early formal verification, unified workflows, and strict gated signoffs are key to avoiding costly respins.
SDVs demand continuous, upstream-first OSS over closed, patch-laden builds. Renesas backs this with VirtIO virtualization…
SDVs demand continuous, upstream-first OSS over closed, patch-laden builds. Renesas backs this with VirtIO virtualization and Sparrow Hawk hardware—OSS as culture, not just cost-cutting.
Beyond touchscreens: Learn how physical feedback drives reliability in automotive, consumer, medical, and industrial…
Beyond touchscreens: Learn how physical feedback drives reliability in automotive, consumer, medical, and industrial electronics applications.
AI agents that operate inside your design software turn requirements into a working mental model you can design against,…
AI agents that operate inside your design software turn requirements into a working mental model you can design against, test, and verify — all within the ECAD environment you already use.
On-device AI enhances retail by enabling real-time processing for robotics, kiosks, and more, offering low latency,…
On-device AI enhances retail by enabling real-time processing for robotics, kiosks, and more, offering low latency, improved privacy, and operational efficiency for a better customer experience.
Hidden upstream dependencies can turn great product designs into costly delays. Discover why component sourcing risk must…
Hidden upstream dependencies can turn great product designs into costly delays. Discover why component sourcing risk must now be factored into early product decisions.
Artificial intelligence data pipelines are placing new pressures on enterprise storage, and data centers must rapidly…
Artificial intelligence data pipelines are placing new pressures on enterprise storage, and data centers must rapidly adapt storage capabilities with SSDs as their backbone.
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