Latest RISC-V Industry Articles

RISC-V’s open architecture enables a shift-left approach to security in embedded systems. Learn how it smooths the way…

RISC-V’s open architecture enables a shift-left approach to security in embedded systems. Learn how it smooths the way for integrating security features and more early in the development cycle.

Learn how open source silicon can provide better security than traditional measures like obscurity, but only if employed…

Learn how open source silicon can provide better security than traditional measures like obscurity, but only if employed correctly, managed well, and backed with appropriate resources.

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the…

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when…

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.

RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.

The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up…

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral…

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed…

This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed to avoid lock-in to specific hardware implementations.

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications…

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and…

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

Part 3 of this series shows examples of the CKB-VM, a RISC-V instruction set based VM, in action in three different ways.

Part 3 of this series shows examples of the CKB-VM, a RISC-V instruction set based VM, in action in three different ways.

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction…

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB,…

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture?…

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.

This article explores the equal importance of software and hardware security for IoT devices and provides actionable…

This article explores the equal importance of software and hardware security for IoT devices and provides actionable steps for securing embedded processors on RISC-V.

RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for…

RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for this technology.

In this article, the author explores and explains his team's process of choosing and utilizing the open-source hardware…

In this article, the author explores and explains his team's process of choosing and utilizing the open-source hardware platform RISC-V in an academic environment.