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How RISC-V Enables Shift-Left Practices for Securing Embedded Systems

How RISC-V Enables Shift-Left Practices for Securing Embedded Systems

RISC-V’s open architecture enables a shift-left approach to security in embedded systems. Learn how it smooths the way for integrating security features and more early in the development cycle.


The 150-Year-Old Principle at the Root of Secure Silicon and Software

The 150-Year-Old Principle at the Root of Secure Silicon and Software

Learn how open source silicon can provide better security than traditional measures like obscurity, but only if employed correctly, managed well, and backed with appropriate resources.


How RISC-V Security Stacks Strengthen Computer Architecture

How RISC-V Security Stacks Strengthen Computer Architecture

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.


Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.


Keeping RISC-V-Based Embedded System Design Flexible with Linux and Zephyr microPlatforms

Keeping RISC-V-Based Embedded System Design Flexible with Linux and Zephyr microPlatforms

This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed to avoid lock-in to specific hardware implementations.


Running Hard Real-Time Applications and Linux on PolarFire SoC

Running Hard Real-Time Applications and Linux on PolarFire SoC

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.


Introduction to the RISC-V Instruction Set CKB-VM and its Requirements

Introduction to the RISC-V Instruction Set CKB-VM and its Requirements

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.


Building Out the RISC-V Ecosystem

Building Out the RISC-V Ecosystem

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.


RISC-V: Opening a New Era of Innovation for Embedded Design

RISC-V: Opening a New Era of Innovation for Embedded Design

This article explores the benefits behind RISC-V's open-source hardware model, discussing it's longevity, portability, and reliability.