Latest System-on-Chip Industry Articles

RISC-V’s open architecture enables a shift-left approach to security in embedded systems. Learn how it smooths the way…

RISC-V’s open architecture enables a shift-left approach to security in embedded systems. Learn how it smooths the way for integrating security features and more early in the development cycle.

Learn how open source silicon can provide better security than traditional measures like obscurity, but only if employed…

Learn how open source silicon can provide better security than traditional measures like obscurity, but only if employed correctly, managed well, and backed with appropriate resources.

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when…

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up…

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral…

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications…

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and…

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB,…

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.

RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for…

RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for this technology.

In this article, the author explores and explains his team's process of choosing and utilizing the open-source hardware…

In this article, the author explores and explains his team's process of choosing and utilizing the open-source hardware platform RISC-V in an academic environment.

Until recently, developers integrating a FPGA fabric with a microcontroller were severely limited in their choice of IP…

Until recently, developers integrating a FPGA fabric with a microcontroller were severely limited in their choice of IP licensing options. Using open-source tools with a RISC-V core in a FPGA is present a solution to that problem.