RISC-V: Transforming the Development of SoC Devices that Combine FPGAs and Microcontrollers

Until recently, developers integrating a FPGA fabric with a microcontroller were severely limited in their choice of IP licensing options, with a closed ecosystem of cores and tools, and little or no ability to port software to other architectures.

This all changed with the RISC-V open instruction set architecture (ISA), which eliminates royalty fees and other limitations of licensed IP cores while launching a new way to develop and future-proof system-on-chip (SoC) systems in today’s rapidly evolving markets. Developers who adopt RISC-V have valuable opportunities to improve design portability, reduce and preserve software investments, and future-proof designs today and in the future. For many different applications, using open-source tools with a RISC-V core in a FPGA is a compelling choice.

A Flexible Foundation for Innovation

The RISC-V processor is founded not on an architecture, but on a fixed instruction set (ISA). The design of the processor micro-architecture is flexible; vendors are free to implement whatever architecture they deem best for their application.  

To enable broad use, the RISC-V Foundation, a non-profit organization controlled by its members, froze the instruction set in 2014 so that the market could dictate their processor architectures. By leveraging the power of the open-source community, developers who use a RISC-V microcontroller solution in an FPGA benefit from hardware portability, software predictability and broad innovation opportunities. 

Portability

Designs that could ramp into high volume will benefit from the portability of RISC-V. Developers can start a design in a FPGA with a soft gate version of a RISC-V core, and then begin shipping the product (for instance, a thermal camera). 

 

Figure 1. Block diagram of a thermal image camera.

 

The RISC-V core in the camera implements all the traditional functions that a microcontroller would support: it configures the image sensor initially and updates the settings periodically when adjustments are required. The RISC-V core also can run the external memory storage stack for setting up the transfer of images or video frames. Because the software will be completely portable across all devices that have a RISC-V core, this creates “royalty-free” processor sub-system register transfer level (RTL) code that can be implemented in any hardware. So, if the volumes of this camera reach high enough levels, simply retarget the RTL source to an ASIC without paying any legal or royalty fees.

Software Stability

Longevity is a major benefit of RISC-V. Developers can count on the fixed ISA and preserve software investments. Industrial designs that are often built to last for several years or sometimes decades can depend on software continuity. With the aforementioned camera example, the software code written and validated for the initial solution can be run on any RISC-V core in the future. The initial manufacturing can be done with a soft RISC-V core in the IGLOO2 FPGA and the code will be completely compatible when an ASIC is created.

Open Source Innovation

The emergence of Linux as a dominant operating system in the embedded market is proof of the power of open source.  One can think of innovation of RISC-V this way:  RISC-V is to hardware designs what Linux is to software. There already exist open-source tools for use with RISC-V, such as Eclipse GUIs, RTOS operating systems, simulation tools, and debug software. The open-source community further benefits users of RISC-V because the pace of innovation can quicken with so many additional developers implementing cores and software tools. Custom micro-architectures can be created and bug fixes/security patches can be identified much more rapidly than with a proprietary processor architecture.

A case in point is Microsemi’s recently rolled out RISC-V ecosystem called Mi-V. The Mi-V ecosystem contains the first FPGA-based open architecture RISC-V IP core and a comprehensive software integrated development environment (IDE) solution, called SoftConsole.

 

 

Figure 2. Microsemi Mi-V RISC-V Ecosystem.

 

SoftConsole is an Eclipse-based IDE hosted on a Linux or Windows platform to provide complete development support, including a C or C++ compiler and complete debugger capability. Designers can develop for a RISC-V IP core in multiple flash-based FPGAs, including Microsemi’s PolarFire and IGLOO2 devices, as well as RISC-V cores from other vendors. Embedded engineers can leverage the benefits of the Mi-V RISC-V IP in their FPGA designs by using the Libero SoC Design Suite. This easy-to-adopt development software enables designers to further optimize the RISC-V RTL core for their specific application.

Designers who want to integrate a microcontroller in a FPGA now have a compelling solution with RISC-V. The advantages of design portability, software stability, and open-source innovation can benefit virtually every application. Customers can also count on the fixed ISA to ensure software compatibility and longevity of the architecture. Using a RISC-V core unleashes a new generation of innovation for SoC designers. 

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