The USC-run service that pioneered multi-project wafers in 1981 now offers a path from shared shuttle runs to full production on GlobalFoundries' FinFET and…
The USC-run service that pioneered multi-project wafers in 1981 now offers a path from shared shuttle runs to full production on GlobalFoundries' FinFET and FD-SOI processes.
The Titanium Edge FPGA family targets constrained edge AI with 50% lower power, compact SiP packages, high-speed MIPI…
The Titanium Edge FPGA family targets constrained edge AI with 50% lower power, compact SiP packages, high-speed MIPI I/O, and robust security/reliability features for intelligent systems.
IBM leveraged its nanostack architecture, a technique that "builds a chip like a city," to pack nearly 100 billion…
IBM leveraged its nanostack architecture, a technique that "builds a chip like a city," to pack nearly 100 billion transistors on a fingernail-sized chip.
The OECD is analyzing the semiconductor industry, focusing on supply chain resilience, global value chain mapping, and…
The OECD is analyzing the semiconductor industry, focusing on supply chain resilience, global value chain mapping, and the impact of rising industrial subsidies on global market competition.
The full-stack platform pairs the IGX Thor compute module with a safety-certified software stack and an accredited…
The full-stack platform pairs the IGX Thor compute module with a safety-certified software stack and an accredited inspection lab, with humanoid maker Agility as the first adopter.
France’s Électronique 2030 program commits €5B+ to revitalize its semiconductor industry. Learn the details of this…
France’s Électronique 2030 program commits €5B+ to revitalize its semiconductor industry. Learn the details of this ambitious effort, and the market challenges it’s facing.
At Computex, Intel described the CPU as the control plane for agentic workloads, pairing new processors and network…
At Computex, Intel described the CPU as the control plane for agentic workloads, pairing new processors and network controllers with fresh details on its inference GPU.
New characterization software delivers 7x throughput gains by combining a predictive AI engine with a purpose-built SPICE…
New characterization software delivers 7x throughput gains by combining a predictive AI engine with a purpose-built SPICE simulator.
An RTL glitch in an eFuse controller can permanently brick costly silicon. This article covers defense-in-depth FSM…
An RTL glitch in an eFuse controller can permanently brick costly silicon. This article covers defense-in-depth FSM design, redundant watchdogs, and formal SVA verification.
In this Tech Guide, learn how the Vishay ISO-AC-VSAO Reference Design enables accurate, isolated high-voltage AC…
In this Tech Guide, learn how the Vishay ISO-AC-VSAO Reference Design enables accurate, isolated high-voltage AC measurement. Watch now to get started!
In this article, we'll learn about several key applications of PLLs in communication systems, including tracking filters,…
In this article, we'll learn about several key applications of PLLs in communication systems, including tracking filters, frequency and phase modulation, and FM and AM demodulation.
An audit finds that the European Chips Act is "very unlikely" to hit the 20% global market target by 2030, citing…
An audit finds that the European Chips Act is "very unlikely" to hit the 20% global market target by 2030, citing fragmented funding, slow progress on FOAKs, and fierce international competition.
SpaceX’s proposed Terafab and Apple's preliminary discussions indicate escalating pressure to expand domestic…
SpaceX’s proposed Terafab and Apple's preliminary discussions indicate escalating pressure to expand domestic semiconductor production.
In this article, we explore when to choose a Class AB or Class D output stage for your piezo amplifier design. We'll also…
In this article, we explore when to choose a Class AB or Class D output stage for your piezo amplifier design. We'll also examine the Class D stage's power supply requirements.
The Hogge phase detector plays multiple roles in CDR circuits. In this article, we'll explore the Hogge detector's…
The Hogge phase detector plays multiple roles in CDR circuits. In this article, we'll explore the Hogge detector's behavior, highlight its main drawbacks, and introduce a different configuration that addresses them.
In this article, we explore the operation of a Class D stage with a capacitive load and how it can be used in piezo…
In this article, we explore the operation of a Class D stage with a capacitive load and how it can be used in piezo amplifier design.
HDLs are formal descriptions of behavior, making them software by definition. Modernizing these outdated tools is key to…
HDLs are formal descriptions of behavior, making them software by definition. Modernizing these outdated tools is key to making FPGA development more accessible and productive for all engineers.
Learn how the Hogge detector addresses the challenges of clock and data recovery (CDR) for data signals with limited…
Learn how the Hogge detector addresses the challenges of clock and data recovery (CDR) for data signals with limited clock information.
We examine the basic requirements of piezoelectric amplifiers and how Class AB operation can meet them.
We examine the basic requirements of piezoelectric amplifiers and how Class AB operation can meet them.
Altera Agilex™ 5 FPGAs and SoCs deliver a powerful balance of high performance, low power, and compact design for…
Altera Agilex™ 5 FPGAs and SoCs deliver a powerful balance of high performance, low power, and compact design for modern embedded and edge computing applications. Watch and learn all about their features, specs, applications, and more!
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