Design and Performance of the Class D Output Stage for Piezo Drivers

Piezo drivers are a necessary part of all piezoelectric systems, including those commonly used for precise positioning and motion control. The optimal design for a piezo driver's output stage depends on the specific application. For example, as we learned in the previous article, the Class AB output stage is best for small-stroke applications that can benefit from the stage's high linearity and low ripple.

In this article, we'll discuss the pros and cons of another widely-adopted output stage: the Class D amplifier. After learning about the principles of its operation, we'll directly apply what we've learned to the case of driving a capacitive piezo load. We'll focus particularly on how the Class D stage can be beneficial to high-power piezo amplifiers.

 

Topology of the Class D Stage

The circuit diagram for the Class D output stage with capacitive load is shown in Figure 1.

 

Figure 1. [click to enlarge] Class D half-bridge switching output stage, used in a voltage feedback amplifier with capacitive piezo load.

 

The Class D output stage uses a different working principle than the Class AB stage. The MOSFETs act as switches, ideally having no voltage drop when they conduct and carrying no current when they are open. The high-side and low-side MOSFET devices are switched ON and OFF at a pulse-width modulation frequency f_PWM = 1/T and with ON-state duty cycle τ/T. When the high-side device is ON, the low-side device is OFF, and vice versa.

The switching node (V_SW) toggles between the positive supply (V_P) and the negative supply (V_N). The information-carrying signal is embedded in the low-frequency component of the signal V_SW.

This design typically uses a second-order LC filter, although more complex lowpass configurations are also possible. In contrast to Class D stages for resistive loads, the piezo load itself (C_l) is part of the LC lowpass filter, together with the parallel capacitance (C_f) and the series inductance (L_f). As we'll discuss later on, the sizing of these components influences both output ripple and the dynamic frequency response of the feedback piezo amplifier.

 

Power Dissipation and Thermal Management

Assuming ideal components, no power will be lost in the output stage. To understand what happens to the energy, imagine a capacitive piezo load that is sinusoidally driven with an ideal Class D output stage. Because of the reactive load, the voltage and current have a quadrature phase relationship, resulting in no net power delivered to the load.

But if no power is dissipated in either the load or the output stage, then where does the energy go? Unlike the Class AB stage, the energy delivered from the power supplies to the load during one-half of the period will simply return to, and be absorbed by, those power supplies during the other half of the period.

This is possible due to the bidirectional nature of the output stage. The design requires that the load source and sink currents both be able to pass through the high-side and low-side parts.

 

Design Implications

In ideal conditions, sinusoidal excitation of a capacitive load only results in back-and-forth energy exchange between the power supplies and load through the Class D output stage. This energy recovery presents a compelling value proposition to piezo applications that require large and/or fast excursions with large piezo loads.

The advantages of this go beyond saving electrical power. Perhaps more importantly, the reactive power doesn't get converted into heat. The benefits for thermal management can be significant. As well as leading to resource savings on the total mass, size, and cost, in some cases it is the only way to reduce thermal stress on power transistors.

 

Practical Considerations

Thus far, we've been discussing an ideal case. A real-world Class D piezo driver will consume power. Primarily, this is due to conduction losses and the charge/discharge cycles of parasitic capacitances in the PWM-switched MOSFETs (see Figure 1). Conduction losses from the on-resistance of the MOSFETs (R_ds,on) and the parasitic resistance of the filter inductance (R_Lf) are calculated as:

$$P_{loss,c}~\approx~I^{2}_{load,rms}(R_{ds,on}~+~R_{Lf})$$

Equation 1.

 

Body-diode conduction losses also play a role (albeit a small one) when the dead time is non-zero. Switching losses and losses related to parasitic capacitances are likewise present, including:

• Gate driver losses (MOSFET input capacitance).
• Reverse recovery losses (MOSFET body diode).
• Output charge losses (MOSFET output capacitance).

These losses are proportional to the PWM switching frequency. While we won't go into further detail here, keep in mind that increasing the PWM frequency of a design always entails a trade-off with power consumption. However, there are still benefits to doing so. As we'll see in the next section, the PWM frequency greatly influences the output ripple.

 

Output Ripple and LC Filter Design

Because of their switching nature, Class D amplifiers suffer from output ripple. This is no different when a capacitive piezo load is connected. The frequency of this residual ripple is dictated by the PWM frequency (f_PWM). The amplitude of the ripple depends on f_PWM and the LC filter at the output.

A structured design approach is required to contain ripple within the performance requirements and to understand how other performance aspects are affected. To map out the design space, let's start with the fundamental equations.

 

LC Filter Design Equations

Assuming that the node V_SW from Figure 1 toggles between –V_s and +V_s (symmetric power supply, V_P = |V_N |) at frequency f_PWM, the maximum peak-to-peak ripple current (ΔI_Lf,ripple) through the filtering inductor (L_f) is equal to:

$$\Delta I_{Lf,ripple}~=~\frac{V_s}{2f_{PWM}~\times~L_f}$$

Equation 2.

 

The maximum peak-to-peak load voltage ripple (ΔV_l,ripple) can be calculated as:

$$\Delta V_{l,ripple}~=~\frac{V_s}{8f_{PWM}^2~\times~(C_f~+~C_l)L_f}$$

Equation 3.

 

where C_f is the parallel filter capacitance and C_l is the load capacitance.

In both of the equations above, we are assuming a simple LC filter with an inductance of L_f and a capacitance equal to the sum of C_f and C_l.

Another equation can be derived by realizing that the output stage filter will have an influence on the small-signal bandwidth (B_f) of the piezo driver. It can be shown that a full piezo driver can be designed to have a third-order Butterworth response with bandwidth:

$$B_f~=~\frac{1}{2 \pi} ~\times~\sqrt{\frac{1}{2 C_{tot} L_f}}$$

Equation 4.

 

where C_tot = C_f + C_l.

The full system bandwidth will also include the impact of the other stages, as well as the voltage feedback shown in Figure 1. More loop gain can always be added to increase the bandwidth.

A system of inequalities can be generated by linking the preceding equations to requirements on ΔI_Lf,ripple, ΔV_l,ripple, and B_f:

$$\frac{V_s}{2f_{PWM}~\times~L_f}~<~\Delta I_{Lf,ripple,required}~\times~\frac{V_s}{8f^2_{PWM}~\times~(C_f~+~C_l)L_f}~<~\Delta V_{l,ripple,required}~\times~\frac{1}{2 \pi}~\times~\sqrt{\frac{1}{2(C_f~+~C_l)L_f}}$$

Equation 5.

 

$$L_fB_{f,required}~<~\Delta V_{l,ripple,required}~\times~\frac{1}{2 \pi}~\times~\sqrt{\frac{1}{2(C_f~+~C_l)L_f}}$$

Equation 6.

 

$$L_fB_{f,required}~<~L_{max}$$

Equation 7.

 

The values we obtain from these equations are limited by the available technology. For example, it is possible to find filter inductors that have a desirable size, current capability, and frequency characteristics. However, they will be limited in the inductance they provide.

 

A Visual Representation of the Design Space

The benefits of this design approach are best illustrated visually. We fill in some realistic values:

• Source voltage of V_S = 150 V.
• PWM switching frequency of f_PWM = 300 kHz.
• Maximum allowed inductor current ripple of ΔI_{Lf,ripple, required} = 4 A (peak-to-peak).
• Maximum allowed output voltage ripple of ΔV_{l,ripple,required} = 1 V (peak-to-peak).
• Small-signal bandwidth of B_f = 3 kHz.
• Maximum inductor value of L_max = 68 μH.

The inequalities in Equations 5 through 7 then turn into allowed design regions in the two-dimensional L_fC_tot plane, as shown in Figure 2.

 

Figure 2. [click to enlarge] Design space in the 2D L_fC_tot-plane for f_PWM = 300 kHz.

 

In the above figure, the solid-colored areas are forbidden design regions. The intersection of allowed regions is hatched in greens. This green-hatched region represents the L_f C_tot-pairs where the ripple and bandwidth will be within the requirements.

Depending on the requirements and parameters (V_s, f_PWM, and L_max come to mind) the allowed region can be larger, smaller, or not exist at all. In the latter case, the requirements are not feasible for the chosen parameters.

Figure 3 shows how the allowed design region can be broadened by increasing f_PWM from 300 kHz to 400 kHz. Increasing f_PWM is beneficial to residual ripple, but poses new challenges for electromagnetic interference (EMI) design, component selection, and possibly power consumption as well.

 

Figure 3. [click to enlarge] Design space in the 2D L_fC_tot-plane for f_PWM = 400 kHz.

 

Once an inductor value (L_f) inside the allowed region is chosen, Figures 2 and 3 also show the compliance range of C_tot = C_f + C_l. If a large range of load capacitances needs to be accommodated, a designer might be forced to put a small filter capacitance in parallel with the load, to decrease the load ripple current for small piezo loads.

This will, however, limit the maximum load current for small piezo loads, which in turn limits the slew rate.

 

Wrapping Up

Class D output stages are particularly interesting for high-power piezo amplifiers. For instance, frequent and/or long mechanical travel applications can profit from energy recovery.

Despite the residual load ripple caused by PWM switching, the Class D stage also proves its worth in cases where the Class AB stage cannot sufficiently dissipate its heat. However, to meet ripple and bandwidth requirements while keeping power consumption and EMI under control, it's important to size the LC filter properly. The structured design approach laid out in this article can help with this.

In the next and last article of this series, we'll discuss one more complication added by the Class D stage's ability to recover energy from a reactive load: its need for a bidirectional DC power supply. We'll then compare the pros and cons of the Class AB and Class D output stages, culminating in an overview of the trade-offs for different use cases.

 

All images used courtesy of Gilles Ackaert