The Core-V Chassis evaluation SoC will feature a CV64A 64-bit core and a CV32E 32-bit coprocessor core as well as 3D and 2D GPUs.
one day ago by Cabe Atwell
Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.
About 5 days ago by Lisa Boneta
Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that offers inference solutions for AI acceleration.
December 03, 2019 by Majeed Ahmad
In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.
November 26, 2019 by Ted Speers, Microchip
This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.
October 29, 2019 by Mouser Electronics
In this article, we’ll first review the basic architecture of a SAR ADC and then take a look at one of its common applications.
October 24, 2019 by Steve Arar
In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.
September 10, 2019 by Ted Marena, Western Digital
Alibaba is set to produce the next generation of Chinese processors with the RISC-V instead of Arm architecture.
July 29, 2019 by Robin Mitchell
RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.
July 23, 2019 by Jothy Rosenberg, Dover Microsystems
This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.
July 09, 2019 by Ted Marena, Western Digital
Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?
July 08, 2019 by Gary Elinoff
The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.
June 20, 2019 by Tommy Lin, Andes Technology
This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.
June 02, 2019 by Stephen St. Michael
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.
May 14, 2019 by Zvonimir Bandić, Western Digital
In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.
April 16, 2019 by Greg Sullivan, Dover Microsystems
Learn more about the Arm computer architecture, including ISA, execution states, and processor families.
April 10, 2019 by Stephen St. Michael
This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed to avoid lock-in to specific hardware implementations.
March 28, 2019 by Trina Watt, Foundries.io
This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.
March 26, 2019 by Tim Morin, Microchip
In this article we’ll look at the defining characteristics of these extremely popular ICs, and then we’ll explore the internal architecture.
March 25, 2019 by Robert Keim
These roadshows will showcase innovative RISC-V implementations from leading RISC innovators.
March 23, 2019 by Gary Elinoff
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