Latest RISC-V Articles and Videos

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Adding Custom Instructions to RISC-V to Boost Performance While Reducing Power and Code Density

The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.

June 20, 2019 by Tommy Lin, Andes Technology

The Advanced Microcontroller Bus Architecture: An Introduction

This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.

June 02, 2019 by Stephen St. Michael

An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

May 14, 2019 by Zvonimir Bandić, Western Digital

Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

April 16, 2019 by Greg Sullivan, Dover Microsystems

The Arm Architecture Explained

Learn more about the Arm computer architecture, including ISA, execution states, and processor families.

April 10, 2019 by Stephen St. Michael

Keeping RISC-V-Based Embedded System Design Flexible with Linux and Zephyr microPlatforms

This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed to avoid lock-in to specific hardware implementations.

March 28, 2019 by Trina Watt, Foundries.io

Running Hard Real-Time Applications and Linux on PolarFire SoC

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

March 26, 2019 by Tim Morin, Microchip

What Is a Microcontroller? The Defining Characteristics and Architecture of a Common Component

In this article we’ll look at the defining characteristics of these extremely popular ICs, and then we’ll explore the internal architecture.

March 25, 2019 by Robert Keim

RISC-V Foundation Hosting Worldwide Series of Getting Started with RISC-V Events

These roadshows will showcase innovative RISC-V implementations from leading RISC innovators.

March 23, 2019 by Gary Elinoff

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

March 20, 2019 by Ted Marena, Western Digital

How to Utilize the RISC-V Instruction Set CKB-VM

Part 3 of this series shows examples of the CKB-VM, a RISC-V instruction set based VM, in action in three different ways.

March 19, 2019 by Xuejie Xiao, Nervos

CKB-VM as a RISC-V Instruction Set: Inspiration, Design, and Benefits

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

March 12, 2019 by Xuejie Xiao, Nervos

Introduction to the RISC-V Instruction Set CKB-VM and its Requirements

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.

March 05, 2019 by Xuejie Xiao, Nervos

How to Write Assembly Instructions for Programming a 32-bit ARM Core with a Raspberry Pi

This article explores the basic instructions needed to program a 32-bit ARM core, while building a foundational understanding of the micro-architecture.

February 26, 2019 by Stephen St. Michael

Arm Releases New Infrastructure and Security Certifications for IoT Devices

Arm's new security certifications and IoT infrastructure platforms plan for one trillion connected devices.

February 25, 2019 by Baker Lawley

Arm Cortex-M Processors Get a Boost towards Machine Learning, DSP in the Age of IoT Edge Computing

Can IoT devices handle edge processing for machine learning and DSP? Arm's newly-announced Helium vector extension for Cortex-M processors aims to facilitate more complex development on the edge.

February 14, 2019 by Baker Lawley

How to Write Assembly Language: Basic Assembly Instructions in the ARM Instruction Set

Learn some basic instructions used in the ARM instruction set used for programming ARM cores.

February 08, 2019 by Stephen St. Michael

What Is a Microarchitecture? Understanding Processors and Register Files in an ARM Core

Learn about the microarchitecture of an ARM processor, including an explanation of the register file and how it functions within a processor.

February 07, 2019 by Stephen St. Michael

Building Out the RISC-V Ecosystem

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.

December 20, 2018 by Markus Levy, NXP Semiconductors

Western Digital SweRVs Towards Open Source with New RISC-V Core, ISS, and Cache Coherency

Is open source changing the way we manage data? Western Digital, a data storage device company, switched to RISC-V's open-source ISA (instruction set architecture) a year ago. This month, they announced a series of open-source, collaborative initiatives that aim to make data more open, from processor cores to memory caches.

December 18, 2018 by Kate Smith