Latest RISC-V Articles and Videos

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A New Partnership Brings Professional Dev Tools to RISC-V Microcontrollers

The joint efforts of GigaDevice and IAR Systems may speed the development time when working with RISC-V.

June 04, 2020 by Gary Elinoff

ISP in a Box: Althea Reimagines Mesh Network Systems

It all starts with firmware that runs a routing protocol, allowing routers to pay each other for bandwidth and automate network configuration.

May 22, 2020 by Kayla Matthews

The International Telecommunication Union Announces a New Architecture That Incorporates MI Mechanisms

Recently, a study into the architecture has been presented by members of the Wireless Networking and AI&ML research groups and described as a “new standard” for telecommunications networks.

May 21, 2020 by Luke James

COVID-19 Puts Spotlight on Open-Source RISC-V Cores, IP

Remote work during this pandemic has shed light anew on the virtues of RISC-V, which has just gotten more accessible.

May 20, 2020 by Antonio Anzaldua Jr.

RISC-V International Partners with GlobalPlatform to Simplify Security Design for IoT Devices and Processors

The collaboration is fuelled by the desire to develop open-source standards that simplify security design for hardware developers and enhance the security of IoT devices.

May 15, 2020 by Luke James

Neural Network Architecture for a Python Implementation

This article discusses the Perceptron configuration that we will use for our experiments with neural-network training and classification, and we’ll also look at the related topic of bias nodes.

January 09, 2020 by Robert Keim

OpenHW Group Announces Multi-core Evaluation SoC Based on the NXP iMX Platform

The Core-V Chassis evaluation SoC will feature a CV64A 64-bit core and a CV32E 32-bit coprocessor core as well as 3D and 2D GPUs.

December 13, 2019 by Cabe Atwell

Microchip Announces First RISC-V-based SoC FPGA to Use Half the Power of Other FPGAs

Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.

December 10, 2019 by Lisa Boneta

AI Hardware Built from a Software-first Perspective: Groq’s Flexible Silicon Architecture

Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that offers inference solutions for AI acceleration.

December 03, 2019 by Majeed Ahmad

How RISC-V Security Stacks Strengthen Computer Architecture

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.

November 26, 2019 by Ted Speers, Microchip

Microchip Dual Core Digital Signal Controllers | New Product Brief

This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.

October 29, 2019 by Mouser Electronics

Learn About SAR ADCs: Architecture, Applications, and Support Circuitry

In this article, we’ll first review the basic architecture of a SAR ADC and then take a look at one of its common applications.

October 24, 2019 by Dr. Steve Arar

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

September 10, 2019 by Ted Marena, Western Digital

Alibaba’s Semiconductor Subsidiary Will Utilize Open-Source RISC-V Core

Alibaba is set to produce the next generation of Chinese processors with the RISC-V instead of Arm architecture.

July 29, 2019 by Robin Mitchell

RISC-V’s Role in Securing IoT-Connected Devices

RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.

July 23, 2019 by Jothy Rosenberg, Dover Microsystems

Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

July 09, 2019 by Ted Marena, Western Digital

CHIPS Alliance Brings Powerful Players into Open Source Hardware Collaboration

Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?

July 08, 2019 by Gary Elinoff

Adding Custom Instructions to RISC-V to Boost Performance While Reducing Power and Code Density

The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.

June 20, 2019 by Tommy Lin, Andes Technology

The Advanced Microcontroller Bus Architecture: An Introduction

This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.

June 02, 2019 by Stephen St. Michael

An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

May 14, 2019 by Zvonimir Bandić, Western Digital