Highlights From RISC-V Summit Europe Point to More RISC-V Abstraction
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
As we wrap up the week of RISC-V Summit Europe, here we'll review how companies this week used the event as a platform to reveal their latest innovations leveraging the open instruction set architecture (ISA). These developments encompass both hardware and software, making them important to designers in a breadth of fields.
Since the first prototype (pictured above), the RISC-V ISA has exploded in popularity thanks to its open and collaborative nature allowing mutual advancements in the field. Image used courtesy of Chiara Coetzee
Since its release in 2015, RISC-V has been an open standard enabling custom hardware and software innovations. The ISA uses preexisting knowledge to speed development times and offers improved flexibility in the design process.
Three highlights from the RISC-V Summit Europe may provide new levels of abstraction for designers who don’t need to operate at the lowest levels of the architecture. This article takes a look at these announcements from the summit and discusses how each innovation provides designers with tools to make the development cycle easier while also improving time to market. In addition, we'll examine the growing RISC-V ecosystem to assess how the ISA will continue to evolve.
Custom Vector Cores
In anticipation of the RISC-V Summit Europe, Semidynamics announced the “largest, fully customizable” RISC-V processor for vector processing. As vector compute becomes increasingly important in AI or computer vision applications, hardware vector support can be an invaluable design tool for many developers working on high-performance systems. Following RISC-V International’s 2021 vector extension, vector processing for the ISA is expected to grow in need.
The Semidynamics Vector Unit offers flexibility and versatility to designers looking to incorporate vector compute capabilities. Image used courtesy of Semidynamics
The Vector Unit from Semidynamics is customizable to fit the application’s needs, allowing designers to scale the datapath lengths, vector lengths, or number formats as necessary. And with integration from 4 up to 32 vector cores in a single unit, even the most computationally intense applications can make use of the Vector Unit. The Vector Units are offered with the Atrevido and Avispado RISC-V cores and demonstrate how versatile the RISC-V ISA can be.
RISC-V Vector Cryptography
Working in tandem with increased vector hardware availability, Codethink has integrated full support for the RISC-V vector cryptography extension set into the emulation software QEMU. And while emulation may not be a direct requirement for vector-enabled cryptographic design to take place, it is a requirement for ratification in the RISC-V specifications.
An example instruction highlights the architecture for the vector extension set, as well as the amount of data handling required to emulate the RISC-V architecture on other systems. Image used courtesy of Codethink
Building off their past experience with RISC-V devices, the Codethink developments in the QEMU emulator will ultimately bring vector cryptography one step closer to RISC-V standardization. Currently, the extension set is in the stable phase, where limited changes are expected, after which the extension set can become frozen and/or ratified.
A group of CHIPS Alliance members, including AntMicro and Google, presented improved digital design tools for integration using RISC-V cores. These tools, namely Verible and Kythe, can be used alongside the Very Efficient and Elegant RISC-V (VeeR) core family to streamline the design process and allow for open collaboration in both intra- and inter-organizational efforts.
The Caliptra block diagram highlights the VeeR core and the number of interfaces that must be accounted for. Using the tools from Antmicro and Google, this design can be expedited. Image used courtesy of Antmicro
These efforts are highlighted by the Caliptra project, which leverages the VeeR core family to provide the security needed in modern-age processors. In addition to the design and verification tools, Antmicro also teased a visual system designer, providing more reasons to believe that RISC-V designers could soon experience a new level of abstraction.
While there are certainly more developments to be covered from the RISC-V Summit Europe, those in this article represent a trend toward increased accessibility and market share for RISC-V processors. This is not to say that analog and digital chip designers will soon be obsolete, but rather that designing a RISC-V processor may soon be an easier task.
With software and hardware innovations, such as visual system design, vector core support, or dedicated RISC-V analog IP, new opportunities for high-level development and integration seem to be on the horizon. This, in addition to a lower barrier to entry into the RISC-V ecosystem, ultimately supports the claim that RISC-V is inevitable.