Agile Analog Brings Analog Subsystems to the RISC-V Ecosystem

When we think of RISC-V, we tend to think about digital electronics and computing. While there is a strong correlation between the two, there are a number of companies that are developing analog IP solutions powered by RISC-V technology. One such company is Agile Analog, which is most well-known for using digital electronics to create configurable analog IP solutions.

This week, Agile Analog announced that it will be launching a complete analog IP subsystem for RISC-V applications, with a heavy focus on battery-powered IoT solutions. In this article, we’ll take a look at the three IP subsystems from Agile Analog and how they’ll benefit the RISC-V community.

 

AgilePMU

The first of three IP subsystems Agile Analog is launching to the RISC-V ecosystem is a series of power management units. Called the agilePMU, these power management units from Agile Analog are highly integrated PMUs for SoCs/ASICs.

A block diagram of the agilePMU. Image courtesy of Agile Analog

 

Designed with an integrated digital controller, two individually programmable low-dropout regulators (LDOs), and an internal bandgap voltage reference, the agilePMU is meant to blend performance with the low-power operation for RISC-V systems. The product is designed to monitor the real-time status of power systems and provide feedback to ensure optimal system performance.

 

AgileSMU 

Along with the PMU offering, Agile Analog will also include a sleep management unit (SMU) called the agileSMU in its RISC-V subsystem macro. 

 

The agileSMU block diagram. Image courtesy of Agile Analog

 

The agileSMU is a low-power solution designed to wake up an SoC from sleep mode in a way that is timely and reliable while maximizing power efficiency. To do this, the agileSMU consists of a programmable oscillator that ranges from 32 kHz to 20 MHz and several low-power comparators (1.5 uA active current) for initiating SoC wake-up. The SMU also includes a power-on-rest (POR) with a start-up time of 10 us and assertion time of 5 us to ensure the startup reset of the SoC.

In an IoT system, this SMU can ensure low-power operation since the main SoC enters sleep mode to conserve power. 

 

AgileSensorIF

The final of the three IP subsystems included in Agile Analog's RISC-V portfolio is its sensor interface product, known as the agileSensorIF.

The agileSensorIF solution is designed to enable sensor interfacing with a primary SoC in an efficient and performant way. The agileSensorIF solution features several integrated blocks, such as ADCs, DACs, low-power analog comparators, and an associated bandgap generator. Additionally, the system features integrated configuration and control logic to enable confirmability and control of the system.

 

Block diagram of the agileSensorIF. Image courtesy of Agile Analog

 

Like most of Agile’s solutions, each of these blocks is configurable, including the number of ADC and DACs as well as their bit-depth and sample rate. Maxed out, the ADC can reach a 12-bit resolution with a sampling rate of 64 MSPS, while the DAC reaches a 12-bit resolution and a rate of 20 MSPS.