Digitally-wrapped Analog Subsystems: The Key to Easy Analog Integration?
Agile Analog has developed digitally-wrapped analog IP subsystems to decrease the design and integration effort of SoCs.
Digital design flow and IP blocks make it easier to reuse and customize designs for different applications. The same, however, cannot be said for analog IP blocks.
To simplify analog IP integration, Agile Analog has launched its digitally-wrapped analog subsystems, including power management, PVT sensing, and sleep management. These subsystems work like a conventional digital IP block, allowing them to be deployed into a digital design flow and connected with standard interfaces.
Concept of Agile Analog’s digitally wrapped IP subsystems
Analog IP Blocks for Digital Design Flow
Digital IP blocks have significantly grown in popularity in the semiconductor industry because a digital design flow follows a structured and linear approach. This approach involves defining inputs and outputs, logic gates selection, and verification through simulation and testing.
In contrast, analog design flow involves an iteration of several cycles depending on the complexity and parameters of the analog circuit block. As a result, the time and effort needed to complete an analog design is high. The complexity also increases with changes in technology. Digital IPs, on the other hand, can be synthesized or optimized for different technology nodes without many modifications.
Analog IPs are still necessary for signal processing, power management, and RF (radio frequency) systems. In these cases, digitally-wrapped analog IPs can provide the best of both worlds. In such a system, analog circuitry is encapsulated in a digital control interface that provides a robust way to control and monitor analog behavior. For example, a digitally-wrapped voltage regulator can include a digital control loop to alter the output power while monitoring the load conditions, temperature, and other parameters.
New Analog IP Subsystems for Agile Analog
Agile Analog recently launched a range of analog subsystems to reduce the time to market, cost, and efforts associated with analog integrated circuit design.
The new customizable analog IPs allow each subsystem block to be tailored for the customer's requirements while covered in a digital wrapper. Furthermore, the subsystems can be modified for customer-specific PDKs (process design kits). Agile Analog claims the process of integrating the IP is simpler because it removes duplicate functions, reduces DRC requirements, and optimizes interconnects. The company also performs verification of analog-to-digital boundary systems.
In Agile Analog's most recent announcement, the company introduced three subsystems: agilePMU for power management, agilePVT for PVT sensors, and agileSMU for sleep management.
The agilePMU is a power management unit for SoCs (System on Chips) and ASICs (Application Specific Integrated Circuits), featuring a power-on reset function, multiple low-dropout regulators, a reference generator, an integrated digital controller, and status monitoring circuitry.
The subsystem provides very high efficiency and optimizes flexibility, according to Agile Analog. The digital controller allows precise control over start-up and shutdown, supply sequencing, and programmable output voltages for each LDO. Status monitors provide real-time information on the status of the subsystem.
The PVT sensor subsystem monitors devices' environmental and electrical characteristics. It incorporates a low-power process, voltage and temperature sensors, a reference generator, an integrated digital controller, and status monitors.
agileSMU is a low-power subsystem to manage the sleep and wake modes of an SoC. It consists of a programmable oscillator for low-frequency SoC operation, RTC, low-power comparators to initiate a wake-up sequence, and a power-on reset. It also has an integrated digital controller and status monitors, similar to the other two subsystems.
All images used courtesy of Agile Analog