“RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes
At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world.
The RISC-V Summit, running from December 12 to 15 this week in San Jose, CA, featured a rich offering of technical and industry keynotes, as well as product launches.
This year's event offered a vivid look at the current status of RISC-V in several aspects, including technology development, industry acceptance, ecosystem, specification work, and more.
A highlight of the RISC-V Summit were its many keynote presentations—six in total, plus several “Spotlight” presentations. That’s too much to cover effectively here, so, in this article we zero in on the highlights from two keynotes that exemplify the state of RISC-V at this moment in time.
RISC-V International CEO Reviews Global Successes
Kicking off the Tuesday RISC-V keynote sessions was Calista Redmond, CEO of RISC-V International. She described the broad scope of success that RISC-V has achieved, and put it into perspective.
In her keynote, Calista Redmond, CEO of RISC-V International, details the huge investments going toward RISC-V. (Click image to enlarge)
“This is our time,” said Redmond. “RISC-V is absolutely the definition of open computing. We have knocked down barriers and we have risen to opportunities. We have overcome challenges and reduced the barriers to entry.”
Next, she made the perhaps bold claim that RISC-V is inevitable. “It's here already,” she said. "It is going across all domains in computing. It is inevitable.” This intriguing notion of RISC-V being inevitable was later echoed and fleshed out in Krste Asanovic’s keynote, which we examine below.
Redmond then turned to discussing the global reach that RISC-V has achieved. “RISC-V is already seen in 10 billion cores globally,” she said. "Innovation is accelerating across all domains, from the lowest power to the highest performance. We’re seeing collective investment and understanding around the world. This ranges from companies investing and pivoting their strategies to RISC-V, to entire nations and regions investing in RISC-V.”
Looking at the industry and business perspective, Redmond said that tens of billions of dollars have been invested in RISC-V. “We see companies like Intel planting a billion dollar flag on RISC-V,” she said. "We see companies like SiFive, MIPS, Alibaba, and Andes committing entire roadmaps to RISC-V.”
“This [RISC-V] is a strategic, long term, durable choice. This is not a choice to meet quarterly metrics. This is a choice for the future of computing, for the future of those companies.”
Remond further pointed out that billions in investment has also been coming in from governments around the world. “We earlier this year saw India commit to RISC-V,” said Redmond. "And in the European Union, we’ve seen many different calls for tender (contracts). I think one just came out last week. These are investments majoring on RISC-V, majoring on the potential to invest locally but engage globally.”
Venture capital investment is high as well, says Remond. “We've tracked more than $2 billion in venture capital alone invested in RISC-V, and there's billions more in the community investment.”
Wrapping up her talk, Redmond doubled down on the message that RISC-V is the future.
“RISC-V is everywhere. RISC-V is redefining computing. And that's not just for this quarter. This is for the next era of computing. Generations to come are pivoting quickly to RISC-V, and I hope you will engage with us.”
Krste Asanović Gives the RISC-V “State of the Union”
Leading off the Wednesday RISC-V Summit keynotes was Krste Asanović. A figure that looms large in the RISC-V world and its history, Krste Asanović heads the free RISC-V ISA project at Berkeley, is Chairman of the RISC-V Foundation, and is Chief Architect and co-founder of SiFive.
At the heart Asanović’s talk was laying out his case for the “why” behind the “RISC-V is inevitable” idea, and what it means. “Reinforcing what Calista said yesterday, I want to start out really by giving you a public service announcement,” he said. "It's really important that you get this. RISC-V is inevitable. RISC-V is going to have the best processors. And RISC-V is going to have the best ecosystem.”
In his RISC-V Summit keynote, Krste Asanović uses the example of network standards as an argument for why the industry will eventually coalesce around RISC-V.
To put things into perspective, Asanović made use of the historical analogy of how networking coalesced down from multiple technology standards into a single standard. “There used to be a lot of competing proprietary standards in networks: DECnet, Token Ring, AppleTalk, FDDI,” he said. "They've all been replaced by Ethernet: a single open standard anybody can use.”
In a similar way, according to Asanović, the real reason why RISC-V is inevitable is not just about its technical merits. While he admits he’s biased, he does claim that RISC-V is a wonderful instruction set architecture (ISA), but it goes beyond that. “The real reason is that the industry wants the open standard ISA business model,” says Asanović.
"All the technical stuff in RISC-V is amazing, but it's really this change in the business model that makes RISC-V inevitable. And just think about this: Once you move to a high-quality open standard, you never go back to sole-source proprietary standards.”
Competition Means RISC-V Will Rise to the Top
To back up his second claim, that “RISC-V will have the best processors,” Asanović explained his reasoning. “RISC-V will have the best processors and there's a couple of major contributors to why that is going to be true, or is already true,” he says.
The first point is RISC-V’s inherent technical advantages. “Now that we see high-end RISC-V designs being completed, fabricated, and mapped to the newest technology, we're seeing that there does seem to be inherent ISA advantages to RISC-V over the others,” says Asanović.
“We're still early days in quantifying this, but I think you're going to start to seeing a lot of very interesting comparisons coming out showing you that RISC-V allows you to build the most efficient cores at any design point—whether you're going after highest performance, best energy efficiency, or smallest area.”
Meanwhile, Asanović explained how the open-source nature of the ISA gives it an inherent advantage. “There are many vendors competing for sockets, for various design wins, “ he says. “Competition drives innovation. So, as you have all these vendors chasing these sockets, it's not just one vendor. You have many.”
Specialization is another twist on that idea. Those RISC-V vendors aren't all competing for the same kinds of socket. “There are specialized vendors going after certain markets,” he says.”So they focus their energy on servicing the needs of these smaller niches in a way that a large single vendor wouldn't be able to. And so this is why you're going to have the best processors in RISC-V land.”
Asanović lists the many vendors working on high-performance RISC-V superscalar out-of-order vector-capable application cores.
Asanović says he sat down and tried to make a list of all the companies who are building RISC-V superscalar out-of-order vector-capable application cores (see image above). “It’s a long list,” he says. “All these folks, they've hired lots of outstanding engineers. They're all busy working away on designs and they're going to be competing. This is part of the open standard. It opens us up to competition, so these guys are going to be building the best processors out there.”
Ecosystem Rides RISC-V's Wave of Success
For his final point, Asanović made the case for why he thinks RISC-V will ultimately have the best ecosystem. This addresses a key issue of RISC-V. Many have been skeptical about whether RISC-V could gain acceptance when competing with other well established processor architectures in the industry.
Interestingly, to address this question, Asanović argues that RISC-V’s ecosystem is tied directly to his first two points—that RISC-V is inevitable and that it will have the best processors. “Everybody's worried about how we fill in the gaps and everything,” he says. “But as RISC-V claims the largest number of players, with almost everybody's moving to RISC-V, that's the force that's going to drive development of the ecosystem.”
Meanwhile, says Asanović, the other big factor is that the performance of RISC-V will attract software developers. “If you have the most energy efficient processor core, if your earbuds have twice the battery life of your competitors' earbuds, that's kind of important, right?” he says. “So, software likes to run on the best hardware.”
“The best hardware will be the best processors. And the best processors will be RISC-V because RISC-V is inevitable. So software is going to want to run on that hardware and we're starting to see that.”
Asanović remarked that RISC-V continues to capture more and more market segments. “Previous times when I gave a talk like this, people would say, ‘Well, RISC-V is good for microcontrollers, good for embedded, good for IoT, but it will never be up in the data center class’,” he said. “I had to bite my lip a little because I was aware of all these design teams working on those kinds of high-end systems.”
“This year is where you will hopefully see that illusion disappearing. The illusion that RISC-V is only for some subset of the space. RISC-V is going to be everywhere, doing everything, and doing it better than the current architectures.”
Is the Hype Hurdle Now in the Rear View Mirror?
It’s clear that RISC-V has come a long way, and has made huge progress even in this past year. Skepticism about its ecosystem and its viability for some uses now seems to be fading. The momentum behind the open ISA is huge.
These two RISC-V Summit keynotes both offer data regarding RISC-V’s success and a strong case for its ever-broadening acceptance. “Inevitable” may be a bold claim to make, but the stars for this technology seem to be aligning on all fronts.
All images from All About Circuits’ (virtual) attendance at the RISC-V Summit
What do you think of RISC-V? Do you see the technology in your future design plans? How do you feel about the current and future ecosystem surrounding RISC-V? Please let us know in the comments below!