4 Highlights From the RISC-V Summit North America

Four companies, including Andes Technology, RISC-V International, Arteris, and Codasip, made significant announcements at tlast week's RISC-V Summit in Santa Clara, California. The two-day summit provided a forum for education, information, and discussion around the fast-growing RISC-V technical community.

Panelists at the RISC-V Summit. Image used courtesy of RISC-V International

1. Andes Technology Invests in Automotive Safety

At the show, Andes launched a new automotive RISC-V processor, the AndesCore D45-SE, targeting ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification.

Block diagram of AndesCore D45-SE. Image used courtesy of Andes Technology

The AndesCore D45-SE is a 32-bit, eight-stage and dual-issue RISC-V processor. The chip is an outgrowth of the in-production D45 processor that has been enhanced for automotive applications. The processor supports RISC-V GCBP extensions, including single/double precision floating point unit, 16-bit compression, bit manipulation, and packed SIMD/DSP extensions.

The design also comes with Andes extensions and safety features to meet the certification requirements. Such features include an additional processor core and comparators for self-diagnosis, ECC memory error correction, bus protection, and hardware stack protection. The D45-SE benchmarks at 6.12 Coremark/MHz, as does the conventional D45. The -SE can run its two cores independently for greater reliability and safety.

The D45-SE processor is certified for critical applications such as millimeter-wave radar sensors, around-view monitor systems (AVMS), vehicle instrument clusters, powertrain DCU, infotainment DCU, and front/rear differential applications.

2. RISC-V International Standardizes 64-bit With RVA23

The RISC-V International organization announced the ratification of RVA23, the 64-bit RISC-V implementation profile standard. The RVA23 profile has vector extensions for math-intensive workloads such as artificial intelligence/machine learning (AI/ML), cryptography, enterprise hardware systems, and operating systems. The new features are a part of the move to make RISC-V a viable option in more demanding settings.

While RISC-V provides flexibility in processor architecture design, this flexibility can pose compatibility issues. Profiles ensure silicon commonality and software compatibility across different vendor implementations of the RISC-V instruction set architecture (ISA). The RVA23 profile does this for 64-bit RISC-V implementations. Software portability is important to the growth of RISC-V as a viable industry processor architecture. Although all RISC-V processors share some base architecture commonality, the specification includes the base and many potential extensions. The profiles specify a set of mandatory extensions that all software developers can assume will be present. Non-mandatory extensions enable customization for specific applications without compromising on core standard functionality.

In addition to the math-intensive vector extensions, the RVA23 also comes with a hypervisor extension that offers virtualization—a key requirement for enterprise and cloud computing implementations.

3. Arteris Partners With SiFive for RISC-V SoC IP

Arteris announced the addition of the SiFive P870-D RISC-V CPU to its system-on-chip (SoC) IP library. The pre-verified solution reduces design risk for data center hardware developers looking to address high-performance application requirements. The Arteris SoC is based on its proprietary scalable cache-coherent network-on-chip (NoC) interconnect IP. The high-speed NoC IP reduces latency between processing units in the SoC. By combining the SiFive RISC-V IP with the Arteris technology, SoC developers have a pre-verified high-performance RISC-V core option.

Pipeline diagram of SiFive's P870. Image used courtesy of Chips and Cheese

The Arteris/SiFive offering supports the advanced microcontroller bus architecture (AMBA) coherent hub interface (CHI) protocol. AMBA CHI is an open standard for chip interconnect specifications used by many SoC solutions. SoCs are frequently the scaling arbiter for data center cluster systems. The high-speed AMBA CHI compatible interconnect architecture and RISC-V core bring data center-targeted SoC development to the RISC-V ecosystem. With the built-in support, chip designers have assurance that the end result will have familiarity, compatibility, and interoperability for data center buildouts.  

4. Codasip Donates RISC-V CHERI SDK

Codasip announced the donation of its CHERI software development kit (SDK) to the community-interest organization CHERI Alliance. Capability Hardware Enhanced RISC Instructions (CHERI) is a security technology that protects systems against pointer-based memory attacks. According to Codasip, memory attacks have represented roughly 70% of cyber-attacks over the past 20 years.

The CHERI architecture extends standard RISC-V processor instruction set architectures (ISAs) to address the vulnerability of C language pointers. CHERI replaces pointers with alternatives that have solid boundaries between different software functions. By isolating and replacing pointers, CHERI can significantly reduce the C and C++ code’s vulnerability to pointer-based memory attacks.

CHERI was originally developed as a joint research project between Cambridge University and SRI International. It has since received funding from the U.S. Defense Advanced Research Projects Agency (DARPA), UK Research and Innovation (UKRI), and other organizations. Codasip released a CHERI-compatible licensable processor in 2023. In this latest move, Codasip has donated its CHERI SDK to the CHERI Alliance to ensure greater availability to the RISC-V developer community. The SDK is available for download on the CHERI Alliance GitHub site.