RISC-V is a free and open Instruction Set Architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building a collaborative community of software and hardware innovators powering innovation at the leading edge of technology.
These coordinated roadshows will be taking place in three areas: the USA, China and the EMEA (Europe, The Middle East and Africa).
North America Roadshow
Participating Companies include Andes Technology, Antmicro, Dover Microsystems, Hex Five, Imperas, Microchip Technology, SiFive and Western Digital.
- Boston – Waltham: April 1 at the Conference Center at Waltham.
- Austin: April 2 at the Commons Conference Center.
- Irvine: April 3 at AV Irvine.
- Bay Area: April 4 at Western Digital in Milpitas.
Click here for information about specific topics and times.
Image courtesy RISC-V Foundation.
Participating Companies will include Alibaba Group, Andes Technology, CloudBEAR, Codasip, GreenWaves Technologies, Nervos, Nuclei System, NXP, PerfXLab, SiFive, Syntacore, Tangram, UC TECH IP and UltraSoC.
- Shenzhen: May 6 at the Crowne Plaza Landmark Shenzhen.
- Chengdu: May 8 at the Sheraton Chengdu Lido Hotel.
- Beijing: Stay tuned for details.
- Shanghai: Stay tuned for details.
- Hangzhou: Stay tuned for details
Click here to get the specifics for the China agenda.
The Timeliness of RISC
RISC stands for Reduced Instruction Set Computer. A significant advantage that it offers over complex instruction set computers (CISC), is that RISC takes fewer clock cycles to execute an instruction.
The two most powerful mantras in the electronics industry today are to use less power and take up less real estate.
These are areas where RISC devices offer very significant advantages for designers of products for the IoT and for wearables, as prime examples. For these reasons, RISC chips are one of the most active areas of development in electronics today.