Is 2017 the Year that RISC-V Will Catch on?

RISC-V's been around for a while but it hasn't achieved the popularity it arguably deserves. Here's a look at the ISA (instruction set architecture) market and the challenges open-source ISAs face.

In 2014, the departments of Electrical Engineering and Computer Sciences at the University of California, Berkley published a white paper titled “Instruction Sets Should Be Free: the Case for RISC-V”. The primary thesis of the paper is that there is no technical reason why an ISA should not be open source.

In the same paper, the team identified the Reduced Instruction Set Computer (RISC) as the most viable platform for an open source ISA due to its commercial success and sophistication compared to some of the other alternatives, such as the Very Long Instruction Word (VLIW) and Complex Instruction Word Computing (CISC).

Since then, the group has formed the RISC-V Foundation (est. 2015) and has been working on developing the open-source ISA for use in research and academic settings. Most recently, the foundation has also been advocating it as the new standard in commercial applications.

But there are mixed feelings on the viability of RISC-V architecture in becoming the new standard ISA. Can RISC-V become the new industry standard or are there too many obstacles?

The Case for Open-Source ISA

The team from UC Berkley’s vision for an open-source ISA involved learning from the mistakes of past ISAs to produce one that is much cleaner and sophisticated. Among some of the improvements, RISC-V boasts:

• Completely open-source, independent of licensing, and not at risk of becoming obsolete if the company that owns it goes defunct
• Independent of microarchitecture style or implementation
• Supports the 2008 IEEE-754 floating point standard
• Supports 32-bit, 64-bit, and 128-bit address spacing
• Can be used in multi-core, heterogeneous processor systems
• A variable length instruction to accommodate the need for longer instructions, or compact ones

RISC-V was selected as the recipient of the “Best Technology Award” for 2016 by the Linley Group, a technology analysis and strategic consulting company. The recognition indicates that the company sees RISC-V as having high potential for impacting the future of design.

At the end of 2016, SiFive—founded by the same creators that developed RISC-V—successfully crowdfunded the first RISC-V based development kit, the HiFive. The campaign appeared to target both at-home hobbyists and hackers, as well as more commercially focused endeavors with offers to customize RISC-V based SoCs.

Further, at Embedded World 2017 held in Berkley, California from March 14 to 16, several companies demonstrated RISC-V being used in their products. This included Microsemi demonstrating RISC-V FPGA solutions, Codasip demonstrating embedded processors for SoC designs, UltraSoC demonstrating RISC-V processor support in their analysis and debugging infrastructure, and Antmicro which demonstrated their AXIOM 4K camera which was developed using the SiFive platform.

 

 

The RISC-V Foundation has also been hosting workshops to encourage the adaptation of the ISA and keep interested parties up-to-date on the most recent developments. The next workshop will take place from May 8 to 11 in Shanghai, China and will open with an “Introduction to RISC-V” session, aimed at individuals or companies that are new to the ISA

Challenges and Criticisms

While the idea of an open-source ISA, open to a world of developers, and free from licensing fees seems like a perfectly good idea, RISC-V certainly has its critics.

One criticism is that the original comparison in the UC Berkley white paper is flawed because it bases the success of RISC primarily over alternatives on the number of CPUs sold using the ISA (largely tablets and mobile phones). When it comes to personal computers, x86 (used by AMD and Intel) remains king.

Many companies are also already deeply ingrained into ARM ISAs and the transition would take resources and time (and ultimately, money). If the current methods work, there may not be enough reason to make the transition, especially when current fees to license ARM are not particularly significant overall. For smaller companies, while the lack of licensing fees and high customizability is certainly appealing, being able to pay for the labor for engineers and developers to actually customize and implement it may ultimately be too much of a burden for it to be adopted.

ARM is also ubiquitous, with a very well understood, well-known lineup of solutions available, years of development already behind them, and readily available support. It is very hard to challenge a well-established platform without significant advantages over it.

 

Image courtesy of ARM.

OpenRISC

The RISC-V Foundation is not the first to explore the possibilities of an open-source ISA. Before RISC-V, there was OpenRISC. OpenRISC has a head start of over a decade on RISC-V, and so has a lot more development and resources available currently. 

One of the first differences to note is that OpenRISC is licensed under an LGPL (hardware) and GPL (models and firmware), versus RISC-V which is licensed via BSD.

The former allows open use of software and hardware, but anything developed using the platform must also be licensed similarly. However, this means there is a lot more support available for any product developed using the platform. The latter does not require anything developed using the platform to be licensed the same way, but there is no support available if you run into trouble with it. This is a very basic breakdown.

Several commercial companies have used OpenRISC to some degree, such as Beyond Semiconductor, Dynalith Systems, Flex and Jennic Limited, Samsung, Allwinner Technology, Candence Design Systems, and ÅAC Microtec (used in an educational cube satellite launched by NASA to demonstrate-plug-and play avionics). 

However, despite all the time and development put into OpenRISC, it certainly is far from being a challenger to ARM or other widely used platforms. RISC-V is very forward about its goal of being the ultimate standard and has made significant strides in a relatively short period of time, but it is difficult to say if it can make enough progress soon enough to overtake current competitors. 

ForwardCom (another open-source ISA in the preliminary stages of development) published a comparison of ForwardCom, OpenRISC, RISC-V, x86, and ARM. For clarity, here is the comparison between OpenRISC and RISC-V (as ForwardCom is still in the preliminary stage, and x86 is a CISC implementation):

 

	OpenRISC	RISC-V	ARM
Intellectual Rights	BSD	GPL	Protected by patents
Technology	RISC	RISC	RISC
Level of Standardization	Most of the ABI	Function calling convention	Most of the ABI
Development Status	Defined instruction set; defined software standard; FPGA implementation available	Defined instruction set; partially defined software standard; FPGA implementation available; ASIC chip available	Fully developed and implemented; continuously developed
Instruction Size	32-bits	32-bits, any multiple of 16-bits	32-bits, 16-bits for thumb instruction set
Immediate Constants	16-bit constants, 16-bit relative address; some constants non-contiguous; 26-bit relative jump and call address	Constants do not have power-of-two sizes; some constants non-contigous	Constants do not have power-of-two sizes
Vector Support	No	No	Scalable Vector Extensions (SVE) currently underway
Flags/Branches/Conditions	1-bit flag set by compare instruction; branch instruction is conditional upon flag	Combined compare-and-branch instructions	ALU instructions optionally modify a flags register; instructions can be conditional upon the flags, including jump and call instructions
Built-in Security	No	No	Optional
Memory Management	TLB, Page Tables	TLB, Page Tables	TLB, Two-Level Page Tables
Function Calling Conventions	Return address in link register; parameters in register or stack; some g.p. registers have callee-save status	Return address in general purpose register; parameters in registers or stack; some g.p. registers and some f.p. registers have callee-save status	Return address in link register; parameters in registers or stack; some g.p. registers and some f.p. registers have callee-save status
Assembly Language	Instruction, Destination Operand, Source Operand	Instruction, Register Operand, Memory Operand	Instruction, Register Operand, Memory Operand

Table data courtesy of ForwardCom.

 

While there are many reasons an open-source ISA may not take hold in the commercial world anytime soon, there have been other examples of open-source software that would eventually become commercially successful, including Unix and Linux. Only time will tell if the ISA is next to go open-source.

Feature image courtesy of the RISC-V Foundation.