IBM leveraged its nanostack architecture, a technique that "builds a chip like a city," to pack nearly 100 billion transistors on a fingernail-sized chip.
IBM leveraged its nanostack architecture, a technique that "builds a chip like a city," to pack nearly 100 billion transistors on a fingernail-sized chip.
The OECD is analyzing the semiconductor industry, focusing on supply chain resilience, global value chain mapping, and…
The OECD is analyzing the semiconductor industry, focusing on supply chain resilience, global value chain mapping, and the impact of rising industrial subsidies on global market competition.
France’s Électronique 2030 program commits €5B+ to revitalize its semiconductor industry. Learn the details of this…
France’s Électronique 2030 program commits €5B+ to revitalize its semiconductor industry. Learn the details of this ambitious effort, and the market challenges it’s facing.
At Computex, Intel described the CPU as the control plane for agentic workloads, pairing new processors and network…
At Computex, Intel described the CPU as the control plane for agentic workloads, pairing new processors and network controllers with fresh details on its inference GPU.
New characterization software delivers 7x throughput gains by combining a predictive AI engine with a purpose-built SPICE…
New characterization software delivers 7x throughput gains by combining a predictive AI engine with a purpose-built SPICE simulator.
An audit finds that the European Chips Act is "very unlikely" to hit the 20% global market target by 2030, citing…
An audit finds that the European Chips Act is "very unlikely" to hit the 20% global market target by 2030, citing fragmented funding, slow progress on FOAKs, and fierce international competition.
SpaceX’s proposed Terafab and Apple's preliminary discussions indicate escalating pressure to expand domestic…
SpaceX’s proposed Terafab and Apple's preliminary discussions indicate escalating pressure to expand domestic semiconductor production.
The Hogge phase detector plays multiple roles in CDR circuits. In this article, we'll explore the Hogge detector's…
The Hogge phase detector plays multiple roles in CDR circuits. In this article, we'll explore the Hogge detector's behavior, highlight its main drawbacks, and introduce a different configuration that addresses them.
Learn how the Hogge detector addresses the challenges of clock and data recovery (CDR) for data signals with limited…
Learn how the Hogge detector addresses the challenges of clock and data recovery (CDR) for data signals with limited clock information.
Advanced packaging is at a crossroads due to AI demand. Learn the four emerging paths—CoWoS, CoPoS, glass-core, and…
Advanced packaging is at a crossroads due to AI demand. Learn the four emerging paths—CoWoS, CoPoS, glass-core, and CoWoP—and how to choose the right one for your multi-die system design.
This article explains the importance of incorporating delay into the feedback path of a phase/frequency detector (PFD)…
This article explains the importance of incorporating delay into the feedback path of a phase/frequency detector (PFD) and examines its effect on performance.
Learn how using a phase/frequency detector (PFD) in place of a phase detector improves the acquisition range of a PLL.
Learn how using a phase/frequency detector (PFD) in place of a phase detector improves the acquisition range of a PLL.
Learn about this simple sequential phase detector and how it compares to the XOR gate. We'll also examine some key…
Learn about this simple sequential phase detector and how it compares to the XOR gate. We'll also examine some key limitations and circuit implementations.
This article explores the operation of the simplest digital phase detector: the exclusive-OR (XOR) gate.
This article explores the operation of the simplest digital phase detector: the exclusive-OR (XOR) gate.
The shift to 3D ICs and chiplets demands automated, hierarchical design planning to manage exploding pin counts. Learn…
The shift to 3D ICs and chiplets demands automated, hierarchical design planning to manage exploding pin counts. Learn how Siemens EDA's Innovator3D IC addresses these challenges.
The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article…
The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article introduces a few ways of speeding up this time-consuming process using automation.
Announced today, the new ChipStack AI Super Agent from Cadence automates front end silicon design and verification,…
Announced today, the new ChipStack AI Super Agent from Cadence automates front end silicon design and verification, delivering a 10X productivity increase.
Singulation (wafer dicing) is critical for IC wafer manufacturing. Laser/plasma dicing is replacing mechanical methods.…
Singulation (wafer dicing) is critical for IC wafer manufacturing. Laser/plasma dicing is replacing mechanical methods. Lidrotec's laser-liquid technology offers virtually zero-damage cuts.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
Enjoy this roundup of our favorite All About Circuits research news articles of 2025!
Enjoy this roundup of our favorite All About Circuits research news articles of 2025!
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